Document
PROCESS
Power Transistor
CP309
NPN - Low Saturation Transistor Chip
PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 4 INCH WAFER 6,285 PRINCIPAL DEVICE TYPES CMPT3090L CXT3090L CZT3090L CMXT3090L EPITAXIAL PLANAR 41.3 x 41.3 MILS 9.0 MILS 9.4 x 9.2 MILS 12.8 x 10.2 MILS Al - 30,000Å Ag - 12,000Å
E
B
BACKSIDE COLLECTOR
R1
R4 (22-March 2010)
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www.DataSheet4U.com
PROCESS
CP309
Typical Electrical Characteristics
R4 (22-March 2010)
w w w. c e n t r a l s e m i . c o m
www.DataSheet4U.com
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