Document
WTK4224
Surface Mount Dual N-Channel Enhancement Mode MOSFET
P b Lead(Pb)-Free
DRAIN CURRENT 10 AMPERES DRAIN SOURCE VOLTAGE 30 VOLTAGE
D1 S1 G1 S2 G2
1 2 3 8 7 6
D1 D2 D2
Features:
*Super high dense cell design for low RDS(ON) RDS(ON)<14mΩ @VGS = 10V RDS(ON)<20mΩ @VGS = 4.5V *Simple Drive Requirement *Dual N MOSFET Package *SO-8 Package
Maximum Ratings (TA=25 C Unless Otherwise Specified)
Rating Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (1) (TA =25˚C) (TA =70˚C) Pulsed Drain Current (2) Power Dissipation (1) (TA =25˚C) Maximax Junction-to-Ambient (1) Operating Junction and Storage Temperature Range Symbol VDS VGS ID IDM PD R θJA TJ, Tstg Value 30 Unite V V A A W C/W C
4
5
1
SO-8
+ 20 10 8 30 2 62.5 -55 to 150
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Device Marking
WTK4224=4224SS
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Electrical Characteristics(Tj = 25
Parameter Drain-Source Breakdown Voltage
Breakdown Voltage Temperature Coefficient
Unless otherwise specified)
Min. 30 1.0 Typ. 0.03 16 23 6 14 12 8 34 16 1910 400 280 0.9 Max. 3.0 100 1 25 14 20 15 3070 pF ns nC Unit V V/ V S nA uA uA m Test Conditions VGS=0, ID=250uA Reference to 25 , ID=1mA VDS=VGS, ID=250uA VDS=10V, ID=10A VGS= 20V
Symbol BVDSS
BVDSS / Tj
Gate Threshold Voltage Forward Transconductance Gate-Source Leakage Current
Drain-Source Leakage Current(Tj=25 ) Drain-Source Leakage Current(Tj=70 )
VGS(th) gfs IGSS IDSS
VDS=30V, VGS=0 VDS=24V, VGS=0 VGS=10V, ID=10A VGS=4.5V, ID=7A ID=10A VDS=24V VGS=4.5V VDS=15V ID=1A VGS=10V RG=3.3 RD=15 VGS=0V VDS=25V f=1.0MHz f=1.0MHz
Static Drain-Source On-Resistance Total Gate Charge
2
2
RDS(ON) Qg Qgs Qgd Td(on) Tr Td(off) Tf Ciss Coss Crss Rg
Gate-Source Charge Gate-Drain (“Miller”) Change Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance
2
Source-Drain Diode
Parameter Forward On Voltage2 Reverse Recovery Time
2
Symbol VSD Trr Qrr
Min. -
Typ. 30 24
Max. 1.2 -
Unit V ns nC
Test Conditions IS=1.7A, VGS=0V, Tj=25 IS=10A, VGS=0V dI/dt=100A/ s
Reverse Recovery Charge
Notes: 1. Pulse width limited by Max. junction temperature. 2. Pulse width 300us, duty cycle 2%.
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/W when mounted on Min. copper pad.
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Characteristics Curve
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Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance v.s. Junction Temperature
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Fig 5. Forward Characteristics of Reverse Diode
Fig 6. Gate Threshold Voltage v.s. Junction Temperature 3/5 07-Apr-10
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WTK4224
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Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
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Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
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SO-8 Package Outline Dimensions
Unit:mm
1
L
θ
E1 D 7 (4X) A C 7(4X)
2A
A1
e
B
eB
SYMBOLS
MILLIMETERS MAX MIN
A A1 B C D E1 eB e L
θ
1.75 1.35 0.20 0.10 0.45 0.35 0.18 0.23 4.69 4.98 3.56 4.06 5.70 6.30 1.27 BSC 0.60 0.80 0 8
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