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SCG4500 Dataheets PDF



Part Number SCG4500
Manufacturers Connor-Winfield
Logo Connor-Winfield
Description Synchronous Clock Generators
Datasheet SCG4500 DatasheetSCG4500 Datasheet (PDF)

SCG4500 Series Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Features • Phase Locked Output Frequency Control • Intrinsically Low Jitter Crystal Oscillator • LVPECL Outputs with Disable Function • Dual Input References • LOR & LOL combined alarm output • Force Free Run Function • Automatic Free Run operation on loss of both References A & B • Input Duty Cycle Tolerant • 3.3V dc Power Supply Bulletin Page Rev.

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SCG4500 Series Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Features • Phase Locked Output Frequency Control • Intrinsically Low Jitter Crystal Oscillator • LVPECL Outputs with Disable Function • Dual Input References • LOR & LOL combined alarm output • Force Free Run Function • Automatic Free Run operation on loss of both References A & B • Input Duty Cycle Tolerant • 3.3V dc Power Supply Bulletin Page Revision Date Issued By www.DataSheet4U.com SG026 1 of 16 P08 08 Oct 02 MBatts • Small Size: 1 Square Inch General Description The SCG4500 Series is a mixed-signal phase locked loop generating LVPECL outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. The LVPECL outputs may be disabled. The SCG4500 Series can lock to one of two external references, which is selectable using the SELAB input select pin. The unit has a fast acquisition time of about 1.5 seconds and it is tolerant of different reference duty cycles. The SCG4500 Series includes an alarm output that indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected the alarm with indicate the need for a reference rearrangement. If both references A and B are absent the module will enter Free Run operation. The FRstatus pin will indicate that the module is in Free Run operation. Frequency stability during Free Run operation is guaranteed to ±20 ppm. Additionally the Free Run mode may be entered manually. The package dimensions are 1” x 1.025” x .45” on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloys, 180°C surface mount reflow processes. Maximum Dimension Package Outline Figure 1 Block Diagram Figure 2 10 kΩ FREE RUN STATUS 10 kΩ FORCE FREE RUN 33 Ω ALARM Q 33 Ω REFA REFB 8 KHz PHASE ALIGNER DPFD ANALOG FILTER LOW JITTER VCXO QN SEL AB 10 kΩ 1/N 33 Ω OPTIONAL REFERENCE OUTPUT ENABLE/ TRI-STATE 10 kΩ Model Comparison Table Table 1 Model Dual Input Ref Freq Max Duty Cycle 40/60 40/60 40/60 LVPECL Oscillator Output (Pins 16 & 18) 77.76 MHz,155.52 MHz,125 MHz 155.52 MHz 77.76 MHz,155.52 MHz Notes Basic Model SCG4500 8 kHz/8 kHz www.DataSheet4U.com SCG4510 1.544MHz/1.544MHz SCG4520 19.44 MHz/19.44 MHz *Features which differentiate a model from the base model (SCG4500) are highlighted in boldface color and in the notes column. Preliminary Data Sheet #: SG026 Page 2 of 16 Rev: P08 Date: 10/08/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Absolute Maximum Rating Table 1 Symbol Vcc Vi Ts Parameter Power Supply Voltage Input Voltage Storage Temperature All SCG4500 Models Minimum -0.5 -0.5 -65.0 Nominal Maximum +4.0 +5.5 +100 Units Volts Volts °C Notes 1.0 1.0 1.0 Operating Specifications Table 2 Symbol Vcc Icc To Ffr Fcap Fbw Tjtol Taq Trf DC MTIEsr Parameter Power Supply Voltage Power Supply Current Temperature Range Free Run Frequency Capture/pull-in range Jitter Filter Bandwidth Input Jitter Tolerance (Input Jitter Frequencies ≥ 10 Hz) All SCG4500 Models Minimum 3.135 170 0 -20 -25 31.25 1 100 40 -50 -50 Nominal 3.3 230 1 225 50 Maximum 3.465 280 70 20 25 10 350 60 50 50 Units Volts mA °C ppm ppm Hz µs µs s ps % 6.0, 7.0 ns ns 3.0 8 kHz Ref. units 19.44 MHz Ref. units 4.0 5.0 Notes 2.0 5.0 Acquisition Time Output Rise and Fall Time (20% 80%) Output Duty Cycle MTIE at Synchronization Rearrangement Dynamic Offset Range (0°- 25°) Dynamic Offset Range (25°- 70°) GR-253-CORE.1999 R5-136 Output Jitter Specifications Table 4 Frequency (MHz) 77.76 125.00 155.52 All SCG4500 Models Jitter BW 10 Hz - 1 MHz pS (RMS) m UI 10 Typ. 10 Typ. 10 Typ. 0.776 Typ. 1.250 Typ. 1.556 Typ. SONET Jitter BW 12 kHz - 20 MHz pS (RMS) m UI 1 Max. 1 Max. 1 Max. 0.076 Max. 0.125 Max. 0.156 Max. NOTES: 1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF) 3.0 3db loop response. www.DataSheet4U.com 4.0 From a 20 PPM step in reference frequency at 25°C @ 3.3V 5.0 50-ohm load biased to 1.3 volts. 6.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing. 7.0 If the selected reference is removed system response to the ALARM must be less than 10µs. Preliminary Data Sheet #: SG026 © Copyright 2002 The Connor-Winfield Corp. Page 3 of 16 Rev: P08 Date: 10/08/02 All Rights Reserved Specifications subject to change without notice Input And Output Characteristics Table 3 Symbol Parameter CMOS Input and Output Characteristics Vih High Level Input Voltage Vil Tio Cl Voh Vol Tir Low Level Input Voltage I/O to Output Valid Output Capacitance High Level Output Voltage Low Level Output Voltage In.


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