Document
SCG4000 V3.0 Series Synchronous Clock Generators
PLL
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Application
The Connor-Winfield SCG4000 Series provides high precision phase lock loop frequency translation for the telecommunication applications. SCG4000 Series is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for TDM, PDH, SONET and SDH network equipment. The SCG4000 Series provides a jitter filtered, wander following output signal sychronized to a superior Stratum or peer input reference signal.
Features
• 3.3V High Precision PLL • Tri-State Capability • Active Alarms • Guaranteed Free Run ±20ppm • 1 sec. Acquisition Time
www.DataSheet4U.com
Bulletin Page Revision Date Issued By
SG031 1 of 12 01 30 JULY 02 MBatts
General Description
The SCG4000 Series is a digital phase locked loop generating a LVPECL outputs from an intrinsically low jitter voltage controlled crystal oscillator. The LVPECL outputs may be disabled. The jitter attenuated internal reference, divided down from the output frequency, is also output to a pin. The SCG4000 Series can lock to one of four possible reference frequencies from 8 to 64 kHz, which is selectable using two input select pins. A filtered reference output signal is available at the same frequency. The unit has an acquisition time of about 1 second and it is tolerant of different reference duty cycles. Further features include alarm outputs for Loss-ofReference (LOR) and Loss-of-Lock (LOL). During the LOR alarm, the SCG4000 will also enter a Free Run state, which will guarantee a 20 ppm accurate output. Additionally the Free Run mode may be entered manually. The alarms and reference output may be put into the tri-state high impedance condition for external testing purposes. The maximum package dimensions are 1” x 1.025” x .450” on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloy, 180° C surface mount reflow processes.
Functional Block Diagram
Figure 1
SC G 4 000 S e rie s B loc k D iagram
ALARM D ETE C TIO N Force Free R un (P in 13)
LO L Alarm Output (P in 11) LO R Alarm O utput (P in 12)
Q (P in 18) R eference Input (P in 4) D IV ID E R D PFD AN ALO G FILTE R FRE E R U N CO NTROL VCXO Differential LVP E C L Outputs QN (P in 16)
D IV ID E R
Select A (P in 5) Select B (P in 6) VC X O Enable (P in 1)
CM OS Reference Output (P in 7)
Model Comparison Table
Table 1
Model SCG4000 SCG4010 SCG4030 Input Ref Freq 8-64 kHz 19.44 MHz 8-64 kHz Max Duty Cycle 40/60 40/60 45/55 CMOS Reference Output (Pin #7) = Input Ref Freq. 19.44 MHz = Input Ref Freq. LVPECL Oscillator Output (Pin #16 & 18) 125.0 MHz, 155.52 MHz 125.0 MHz, 155.52 MHz 125.0 MHz, 155.52 MHz Tighter Duty Cycle Notes Basic Model
*Features which differentiate a model from the base model (SCG4000) are highlighted in boldface, color and in the notes column.
www.DataSheet4U.com
Data Sheet #: SG031
Page 2 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Absolute Maximum Rating
Table 2
Symbol Vcc V1 Ts Parameter Power Supply Voltage Input Voltage Storage Temperature
All SCG4000 Models
Minimum 3.0 -0.5 -65 Nominal Maximum 3.6 5.5 150 Units Volts Volts deg. C Notes
Operating Specifications
Table 3
Symbol Vcc Icc To Ffr Fcap Fbw Tjtol Taq Trf Parameter Power Supply Voltage Power Supply Current Temperature Range Free Run Accuracy Capture/pull-in range Jitter Filter Bandwidth Input Jitter Tolerance Acquisition Time Output Rise and Fall Time (20% 80%)
All SCG4000 Models
Minimum 3.135 0 -20 -25 100 Nominal 3.3 230 1 225 Maximum 3.465 280 70 20 25 10 31.25 1.0 350 Units Volts mA °C ppm ppm Hz µs µs s ps SCG4000, SCG4030 SCG4010 2.0 3.0 Notes 1.0
Features
Table 4
Parameter Alarms TDEV MTIE Static Offset Dynamic Offset VCXO Output Logic Type Reference Output Logic Type Package
All SCG4000 Models
Specifications LOR, LOL Status on seperate CMOS Outputs 70 ps (typical) 800 ps (typical) ± 26 ns Maximum ± 20 ns Maximum LVPECL CMOS FR4 SM 1.0" x 1.025" x 0.45" 4.0 5.0 Notes
CMOS Input And Output Characteristics
Table 5
Symbol VIH VIL TIO CO VHO TIR
NOTES: 1.0: 2.0: 3.0: 4.0: 5.0:
All SCG4000 Models
Parameter High Level Input Voltage Low Level Input Voltage I/O to Output Valid Output Capacitance High Level Output Voltage loh = 04mA Input Reference Signal Pulse Width 2.4 0.4 12.5 nS Minimum 2 0 Nominal Maximum 5.5 0.8 10 10 Units V V nS pF Vcc Min. Vcc Max. Notes
VIO Low Level Output Voltage lo1 = 8mA www.DataSheet4U.com
Requires external regulation and filter (22uF, 330 pF) From a 20 ppm offset in reference frequency 50Ω load biased to 1.3V Offset between Reference Input and Reference Output @ room temp. Offset change between Reference Input and Reference Output over temperature range from room temperatur.