HY5S7B2ALFP-H

512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O Specification of 512M (16Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Nov. 2008 1 11 512Mbit (16Mx32bit) Mobile SDR Memory HY5S7B2ALF(P) Series Document Title 4Bank x 4M x 32bits Synchronous DRAM Revision History Revision No. 0.1 1.0 1.1 1.2 Initial Draft Release Insert (Page10) DPD specification [IDD7 : 10uA min] Correct device height (page 53) History Draft Date Nov. 2006 May. 2007 July. 2007 Nov. 2008 Remark Preliminary Rev 1.2 / Nov. 2008 2 11 512Mbit (16Mx32bit) Mobile SDR Memory HY5S7B2ALF(P) Series DESCRIPTION The Hynix HY5S7B2ALF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix 512M Mobile SDRAM is 536,870,912-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock...