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HY5S2B6DLFP-BE Dataheets PDF



Part Number HY5S2B6DLFP-BE
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 4Banks x 2M x 16bits Synchronous DRAM
Datasheet HY5S2B6DLFP-BE DatasheetHY5S2B6DLFP-BE Datasheet (PDF)

HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 History Initial Draft Deleted Preliminary Changed Operation Voltage : 1.65(min) -> 1.70(min) Draft Date Dec. 2003 May. 2004 Feb. 2005 Remark Preliminary This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are.

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HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 History Initial Draft Deleted Preliminary Changed Operation Voltage : 1.65(min) -> 1.70(min) Draft Date Dec. 2003 May. 2004 Feb. 2005 Remark Preliminary This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Feb. 2005 1 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix HY5S2B6DLF(P) series is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It is organized as 4banks of 2,097,152x16. The Mobile SDR provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Mobile SDR also provides for special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks. The Hynix HY5S2B6DLF(P) series has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power reduction by removing power to the memory array within each SDR. By using this feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. FEATURES Standard SDR Protocol Internal 4bank operation ● Voltage : VDD = 1.8V, VDDQ = 1.8V ● LVCMOS compatible I/O Interface ● Low Voltage interface to reduce I/O power ● Low Power Features - PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - Deep Power Down Mode ● ● ● Programmable CAS latency of 1, 2 or 3 Pakage Type : 54Ball FBGA - HY5S2B6DLF : Lead - HY5S2B6DLFP : Lead Free ORDERING INFORMATION Part Number HY5S2B6DLF-SE 105MHz HY5S2B6DLFP-SE 4banks x 2Mb x 16 HY5S2B6DLF-BE 66MHz HY5S2B6DLFP-BE 2 Lead Free LVCMOS Lead 3 Lead Free Clock Frequency CAS Latency Organization Interface 54Ball FBGA Lead Rev. 0.3 / Feb. 2005 2 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM BALL DESCRIPTION 9 8 7 3 2 1 A B C D E F G H J 54 Ball FBGA 0.8mm Ball Pitch 1 VSS DQ14 DQ12 DQ10 DQ8 UDQM NC A8 VSS 2 DQ15 3 VSSQ 7 A B C D E F G H J VDDQ 8 DQ0 9 VDD DQ1 DQ3 DQ5 DQ7 /WE /CS A10 VDD DQ13 VDDQ VSSQ DQ2 DQ11 VSSQ VDDQ DQ4 DQ9 VDDQ VSSQ DQ6 NC VSS VDD LDQM CLK CKE /CAS /RAS A11 A9 BA0 BA1 A7 A6 A0 A1 A5 A4 A3 A2 < Top View > Rev. 0.3 / Feb. 2005 3 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM PAD FUNCTION DESCRIPTIONS Ball Out F2 SYMBOL CLK TYPE INPUT DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDR on the rising edge of CLK Clock Enable : Controls internal clock signal and when deactivated, the SDR will be one of the states among power down, suspend or self refresh Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM Bank Address : Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 Command Inputs : RAS, CAS and WE define the operation Refer function truth table for details Data Mask:Controls output buffers in read mode and masks input data in write mode Data Input/Output:Multiplexed data input/output pin F3 CKE INPUT G9 G7, G8 H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2 F8, F7, F9 F1, E8 A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 A9, E7, J9, A1, E3, J1 A7, B3, C7, D3, A3, B7, C3, D7 E2, G1 CS BA0, BA1 A0 ~ A11 RAS, CAS, WE UDQM, LDQM INPUT INPUT INPUT INPUT INPUT DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC I/O SUPPLY Power supply for internal circuits SUPPLY Power supply for output buffers No connection : These pads should be left unconnected Rev. 0.3 / Feb. 2005 4 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Low Power Synchronous DRAM PASR Extended Mode Register Self refresh logic & timer Internal Row Counter CLK CKE CS RAS CAS WE U/LDQM 2Mx16 BANK 3 Row Active Stat.


HY5S2B6DLFP-SE HY5S2B6DLFP-BE HY5S5B2BLF-6E


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