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PCS3P625Z09B Dataheets PDF



Part Number PCS3P625Z09B
Manufacturers PulseCore Semiconductor
Logo PulseCore Semiconductor
Description Low Frequency Timing-Safe Peak EMI reduction IC
Datasheet PCS3P625Z09B DatasheetPCS3P625Z09B Datasheet (PDF)

May 2008 rev 0.1 PCS3P625Z05B/C PCS3P625Z09B/C High Frequency Timing-Safe™ Peak EMI reduction IC www.DataSheet4U.com General Features • • • High Frequency Clock distribution with TimingSafe™ Peak EMI Reduction Input frequency range: 100MHz - 175MHz Multiple low skew Timing-safe™ Outputs: PCS3P625Z05: 5 Outputs PCS3P625Z09: 9 Outputs • • • • External Input-Output Delay Control option Supply Voltage: 3.3V±0.3V Commercial and Industrial temperature range Packaging Information: ASM3P625Z05: 8 pin .

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Document
May 2008 rev 0.1 PCS3P625Z05B/C PCS3P625Z09B/C High Frequency Timing-Safe™ Peak EMI reduction IC www.DataSheet4U.com General Features • • • High Frequency Clock distribution with TimingSafe™ Peak EMI Reduction Input frequency range: 100MHz - 175MHz Multiple low skew Timing-safe™ Outputs: PCS3P625Z05: 5 Outputs PCS3P625Z09: 9 Outputs • • • • External Input-Output Delay Control option Supply Voltage: 3.3V±0.3V Commercial and Industrial temperature range Packaging Information: ASM3P625Z05: 8 pin SOIC, and TSSOP ASM3P625Z09:16 pin SOIC, and TSSOP • True Drop-in Solution for Zero Delay Buffer, ASM5P2305A / 09A with Peak EMI reduction. PCS3P625Z05 is an eight-pin version, accepts one reference input and drives out five low-skew Timing-Safe™ clocks. PCS3P625Z09 accepts one reference input and drives out nine low-skew TimingSafe™clocks. PCS3P625Z05/09 has a DLY_CTRL for adjusting the Input-Output clock delay, depending upon the value of capacitor connected at this pin to GND. PCS3P625Z05/09 operates from a 3.3V supply and is available in two different packages, as shown in the ordering information table, over commercial and Industrial temperature range. Application PCS3P625Z05/09 is targeted for use in Displays and Functional Description PCS3P625Z05/09 is a versatile, 3.3V Zero-delay buffer designed to distribute high frequency Timing-Safe™ clocks memory interface systems. General Block Diagram PLL CLKIN DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3 CLKIN PLL MUX DLY_CTRL CLKOUTA1 CLKOUTA2 CLKOUTA3 CLKOUTA4 PCS3P625Z05B/C CLKOUT4 S2 S1 Select Input Decoding CLKOUTB1 CLKOUTB2 CLKOUTB3 PCS3P625Z05B/C CLKOUTB4 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. May 2008 rev 0.1 Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves with a 50% duty cycle and as frequencies increase the edge rates also get faster. Analysis shows that a square wave is composed of fundamental frequency and harmonics. The fundamental frequency and harmonics generate the energy peaks that become the source of EMI. Regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from the equipment. In fact, the peak level allowed decreases as the frequency increases. The standard methods of reducing EMI are to use shielding, filtering, multi-layer PCS3P625Z05B/C PCS3P625Z09B/C www.DataSheet4U.com PCBs etc. These methods are expensive. Spread spectrum clocking reduces the peak energy by reducing the Q factor of the clock. This is done by slowly modulating the clock frequency. The PCS3P625Z05/09 uses the center modulation spread spectrum technique in which the modulated output frequency varies above and below the reference frequency with a specified modulation rate. With center modulation, the average frequency is the same as the unmodulat.


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