DatasheetsPDF.com

GS880F36T-14 Dataheets PDF



Part Number GS880F36T-14
Manufacturers GSI Technology
Logo GSI Technology
Description 8Mb Sync Burst SRAMs
Datasheet GS880F36T-14 DatasheetGS880F36T-14 Datasheet (PDF)

Preliminary GS880F18/36T-10/11/11.5/12/14 100 Pin TQFP Commercial Temp Industrial Temp Features • Flow through mode operation. • 3.3V +10%/-5% Core power supply. • 2.5V or 3.3V I/O supply. • LBO pin for linear or interleaved burst mode. • Internal input resistors on mode pins allow floating mode pins. Default to Interleaved Pipelined Mode. • Byte write (BW) and/or global write (GW) operation. • Common data inputs and data outputs. • Clock Control, registered, address, data, and control. • Intern.

  GS880F36T-14   GS880F36T-14



Document
Preliminary GS880F18/36T-10/11/11.5/12/14 100 Pin TQFP Commercial Temp Industrial Temp Features • Flow through mode operation. • 3.3V +10%/-5% Core power supply. • 2.5V or 3.3V I/O supply. • LBO pin for linear or interleaved burst mode. • Internal input resistors on mode pins allow floating mode pins. Default to Interleaved Pipelined Mode. • Byte write (BW) and/or global write (GW) operation. • Common data inputs and data outputs. • Clock Control, registered, address, data, and control. • Internal Self-Timed Write cycle. • Automatic power-down for portable applications. • 100-lead TQFP package -10 -11 -11.5 -12 -14 10ns 11ns 11.5ns 12ns 14ns Flow Through tKQ 2-1-1-1 tCycle 10ns 15ns 15ns 15ns 15ns IDD 225mA 180mA 180mA 180mA 175mA 512K x 18, 256K x 36 8Mb Sync Burst SRAMs 10ns - 14ns www.DataSheet4U.com 3.3V VDD 3.3V & 2.5V I/O broadest access to multiple vendor sources. Boards designed with FT pin pads tied low may be stuffed with GSI’s Pipeline/Flow through configurable Burst RAMS or any vendor’s Flow through or configurable Burst SRAM. Bumps designed with the FT pin location tied High or floating must employ a non-configurable Flow through Burst RAM, like this RAM, to achieve Flow through functionality. 88018/32/36TByte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS880F18/32/36T operates on a 3.3V power supply and all inputs/outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. Functional Description Applications The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. Controls Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive edge triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle.


GS880F36T-12 GS880F36T-14 GS880F18BT-4.5


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)