Document
PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
INTRODUCTION
48-LQFP-0707 S5L9290X is a signal processing LSI for the CD. Digital processing function (EFM demodulation, error correction), spindle motor servo processing, wide capture range DPLL and 1-bit DAC for the CD player are installed in S5L9290X.
FEATURES
• Signal processing part — EFM data demodulation — Frame sync detection, protection, insertion — Sub code data processing (Q data CRC check, Q data register installed) — Error correction (C1: 2 error correction, C2: 4 erasure correction) — Installed 16K SRAM for De-interleave — Interpolation — Digital audio interface — CLV servo control (X1, X2) — Wide capture range digital PLL ( ± 50%) • Digital filter, DAC part — 4 times over sampling digital filter — Digital de-emphasis (can be process the 32kHz, 44.1kHz, 48kHz) — Sigma-delta stereo DAC installed — Audio L.P.F installed
ORDERING INFORMATION
Device S5L9290X01L0R0 Package 48-LQFP-0707 Supply Voltage 2.7V 3.3V (Analog, Internal logic) 2.7V 5.5V (I/O port) Operating Temperature -20°C +75°C
1
www.DataSheet.in
PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
BLOCK DIAGRAM
SQCK SBCK
SOS1 SQDT SBDT
C2PO
DATX
VCO1LF EFMI DPLL
Subcode Out
Digital Out
LOCK SMEF SMDP SMDS WDCK
EFM Demodulator
Interpolator
Digital Filter
CLV Servo
ECC
1-bit DAC
WFCK RFCK C4M XIN ISTAT MLT MDAT MCK MUTE
Timing Generator
16K SRAM PWM
Micom Interface
Address Generator
I/O Interface
LPF
JITB
SADTO LRCKO BCKO
SADTI LRCKI BCKI
LCHOUT VHALF RCHOUT VREF
2
www.DataSheet.in
PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
PIN CONFIGURATION
VDDD_DAC
VDDA_DAC
VSSD_DAC
VSSA_DAC
VDDA_PLL
RCHOUT
LRHOUT
VHALF
SADTI
LRCKI 38
VREF
48 VSSA_PLL VCO1LF 1 2
47
46
45
44
43
42
41
40
39
37 36 BCKO 35 LRCKO 34 SADTO 33 DATX 32 C2PO
VSSD_PLL 3 VDDD_PLL 4 VDDD1_5V 5 XIN XOUT 6 7
S5L9290X
DSP+DAC
48-LQFP-0707
BCKI
31 JITB 30 SBCK 29 VDDD3-5V 28 VSSD2-3V 27 VDDD2-3V 26 MUTE 25 SQDT
VSSD1_5V 8 EFMI 9
LOCK 10 SMEF 11 SMON 12
13 SMDS
14 WDCK
15 TESTV
16 LKFS
17 LKFS
18 RESETB
19 MLT
20 MDAT
21 MCK
22 ISTAT
23 S0S1
24 SQCK
3
www.DataSheet.in
PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
PIN DESCRIPTION
Table 1. Pin Description NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME VSSA_PLL VCO1LF VSSD_PLL VDDD_PLL VDDD1-5V XIN XOUT VSSD1 EFMI LOCK SMEF SMDP SMDS WDCK TESTV LKFS C4M RESETB MLT MDAT MCK ISTAT S0S1 SQCK I/O O I O I O O O O O I O O I I I I O O I Analog Ground for DPLL Pump out for VCO1 Digital Ground Separated Bulk Bias for DPLL Digital Power Separated Bulk Bias for DPLL (3V Power) Digital Power (5V Power, I/O PAD) X'tal oscillator input (16.9344MHz) X'tal oscillator output Digital Ground (I/O PAD) EFM signal input CLV Servo locking status output LPF time constant control of the spindle servo error signal Phase control output for Spindle Motor drive Speed control output for Spindle Motor drive Word clock output (Normal Speed : 88.2KHz, Double Speed : 176.4KHz) Various Data/Clock Input The Lock status output of frame sync 4.2336MHz clock output System Reset at 'L' Latch signal input from Micom Serial data input from Micom Serial data receiving clock input from Micom The internal status output to Micom Subcode sync signal(S0+S1) output Subcode-Q data transfering bit clock input Pin Description
4
www.DataSheet.in
PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
Table 1. Pin Description (continued) NO. 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME SQDT MUTE VDDD2-3V VSSD2 VDDD3-5V SBCK JITB C2PO DATX SADTO LRCKO BCKO BCKI LRCKI SADTI VSSD_DAC VDDD_DAC RCHOUT VSSA_DAC VREF VHALF VDDA_DAC LCHOUT VDDA_PLL I/O O I I O O O O O O I I I O O O O Function Description Subcode-Q data serial output System mute at 'H' Digital Power (3V Power, Internal Logic) Digital Ground (Internal Logic) Digital Power (5V Power, I/O PAD) Subcode data transfering bit clock Internal SRAM jitter margin status output C2 pointer output Digital audio data output Serial audio data output (48 slot, MSB first) Channel clock output Bit clock output Bit clock input Channel clock input Serial audio data input (48 slot, MSB first) Digital Ground for DAC Digital Power for DAC (3V Power) Right-Channel audio output through DAC Analog Ground for DAC Referance Voltage output for bypass Referance Voltage output for bypass Analog Power for DAC (3V Power) Left-Channel audio output through DAC Analog Power for PLL (3V Power)
5
www.DataSheet.in
PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
MAXIMUM ABSOLUTE RATINGS
Item Power supply voltage Input supply voltage Operating temperature Storage temperature Symbol VDD VI TOPR TSTG Rating 3V: -0.3 3.8 5V: -0.3 7.0 3V I/O: -0.3 VDD + 0.3 5V I/O: -0.3 5.5 -20 75 -40 125 Unit V V °C °C
ELECTRICAL CHARACTERISTICS
OPERATING CONDITION
Item Power supply voltage
Symbol VDD TOPR
Operating Range 3V: 2.7 3.3 5V: .