(CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
Description
18-Mbit QDR II SRAM 4-Word Burst Architecture
Features
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CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ®
Configurations
CY7C1311JV18 – 2M x 8 CY7C1911JV18 – 2M x 9 CY7C1313JV18 – 1M x 18 CY7C1315JV18 – 512K x 36
Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions 300 MHz Clock for High Bandwidth 4-word Burst for reducin...
