Document
SSM9971GD
Dual N-channel Enhancement-mode Power MOSFETs
PRODUCT SUMMARY
BVDSS R DS(ON) ID
DESCRIPTION
The SSM9971GD acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. The SSM2310GD is supplied in an RoHS-compliant PDIP-8 package, which is widely used for medium power commercial and industrial applications, where throughhole insertion into the board is required.
60V 50mΩ 5A
Pb-free; RoHS-compliant SO-8
D2 D2 D1 D1
G2
PDIP-8
S1
S2 G1
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VGS ID IDM PD TSTG TJ Parameter Drain-source voltage Gate-source voltage Continuous drain current Pulsed drain current
1,2
3
3 ,
Value 60 ± 25 T A = 25°C TA = 70°C 5 3.2 20 2 0.016 -55 to 150 -55 to 150
Units V V A A A W W/°C °C °C
Total power dissipation , TA = 25°C Linear derating factor Storage temperature range Operating junction temperature range
THERMAL CHARACTERISTICS
Symbol RΘJA Parameter Maximum thermal resistance, junction-ambient
3
Value 62.5
Units °C/W
Notes:
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on a square inch of copper pad on FR4 board; 90°C/W when mounted on the minimum pad area required for soldering.
10/16/2005 Rev.3.1
www.SiliconStandard.com
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SSM9971GD
ELECTRICAL CHARACTERISTICS
Symbol BVDSS Parameter Drain-source breakdown voltage
Breakdown voltage temperature coefficient
(at Tj = 25°C, unless otherwise specified)
Test Conditions VGS=0V, ID=250uA Reference to 25°C, ID=1mA VGS=10V, ID=5A VGS=4.5V, ID=2.5A Min. 60 1 Typ. 0.06 7 32.5 4.9 8.8 9.6 10 30 5.5 1560 156 110 Max. Units 50 60 3 1 25 ±100 V V/°C mΩ mΩ V S uA uA nA nC nC nC ns ns ns ns pF pF pF
∆ BV DSS/∆ Tj
RDS(ON)
Static drain-source on-resistance2
VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Gate threshold voltage Forward transconductance
VDS=VGS, ID=250uA VDS=10V, ID=5A
Drain-source leakage current
VDS=60V, VGS=0V
VDS=48V ,VGS=0V, Tj = 70°C VGS=±25V ID=5A VDS=48V VGS=10V VDS=30V ID=5A RG=3.3Ω , VGS=10V RD=6Ω VGS=0V VDS=25V f=1.0MHz
Gate-source leakage current Total gate charge
2
Gate-source charge Gate-drain ("Miller") charge Turn-on delay time Rise time Turn-off delay time Fall time Input capacitance Output capacitance Reverse transfer capacitance
2
Source-Drain Diode
Symbol VSD trr Qrr Parameter Forward voltage
2
Test Conditions IS=1.6A, VGS=0V IS=5A, VGS=0V, dI/dt=100A/µs
Min. -
Typ. 29.2 48
Max. Units 1.2 V ns nC
Reverse-recovery time
Reverse-recovery charge
Notes:
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%.
10/16/2005 Rev.3.1
www.SiliconStandard.com
2 of 5
SSM9971GD
35 35
T A =25 C
30
o
ID , Drain Current (A)
ID , Drain Current (A)
25
10V 6.0V 4.5V
T A =150 C
30
o
10V 6.0V 4.5V
25
20
20
15
15.