256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
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256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
256M (32Mx8bit) Hynix SDRAM Memory
Memory Cell A...
Description
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256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
256M (32Mx8bit) Hynix SDRAM Memory
Memory Cell Array
- Organized as 4banks of 8,388,608 x 8
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1
Synchronous DRAM Memory 256Mbit H57V2582GTR Series
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Document Title
256Mbit (32M x8) Synchronous DRAM
Revision History
Revision No. 0.1 1.0 History Preliminary Release Draft Date Jun. 2009 Aug. 2009 Remark
Rev 1.0 / Aug. 2009
2
Synchronous DRAM Memory 256Mbit H57V2582GTR Series
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111
DESCRIPTION
The Hynix H57V2582GTR Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 8,388,608 x 8 I/O. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Synchronous DRAM provides for programmable read or write Burst length of Programmable bur...
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