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LP62S2048-T Dataheets PDF



Part Number LP62S2048-T
Manufacturers AMIC Technology
Logo AMIC Technology
Description 256K X 8 BIT LOW VOLTAGE CMOS SRAM
Datasheet LP62S2048-T DatasheetLP62S2048-T Datasheet (PDF)

LP62S2048-T Series 256K X 8 BIT LOW VOLTAGE CMOS SRAM Features n Power supply range: 2.7V to 3.3V n Access times: 70/100 ns (max.) n Current: Low power version: Operating: 30mA (max.) Standby: 50µA (max.) Very low power version: Operating: 30mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retentio.

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LP62S2048-T Series 256K X 8 BIT LOW VOLTAGE CMOS SRAM Features n Power supply range: 2.7V to 3.3V n Access times: 70/100 ns (max.) n Current: Low power version: Operating: 30mA (max.) Standby: 50µA (max.) Very low power version: Operating: 30mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) and 36-pin CSP packages General Description The LP62S2048-T is a low operating current 2,097,152bit static random access memory organized as 262,144 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOP n TSOP/(TSSOP) n CSP (Chip Size Package) 36-pin Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 32 31 30 29 28 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 17 32 H A9 A10 A11 A12 A13 A14 1 2 A1 A2 3 CE2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O1 I/O2 VCC GND NC OE CE1 A17 A16 A15 I/O3 I/O4 16 1 LP62S2048V-T (LP62S2048X-T) 6 7 8 9 10 11 12 13 14 15 16 27 26 25 24 23 22 21 20 19 18 17 A B C D E F G A0 I/O5 I/O6 GND VCC I/O7 I/O8 (August, 2001, Version 1.0) LP62S2048M-T Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 5 WE 21 I/O1 6 CE2 22 I/O2 7 A15 23 I/O3 8 VCC 24 GND 9 A17 25 I/O4 10 A16 26 I/O5 11 A14 27 I/O6 12 A12 28 I/O7 13 A7 29 I/O8 14 A6 30 CE1 15 A5 31 A10 16 A4 32 OE 1 AMIC Technology, Inc. LP62S2048-T Series Block Diagram A0 VCC GND A15 A16 A17 ROW DECODER 1024 X 2048 MEMORY ARRAY I/O1 INPUT DATA CIRCUIT COLUMN I/O I/O8 CE2 CE1 OE WE CONTROL CIRCUIT Pin Description - SOP Pin No. 1 - 12, 23, 25 - 28, 31 13 - 15, 17 - 21 16 22 24 29 30 32 Symbol Description Pin Descriptions - TSOP/TSSOP Pin No. 1 - 4, 7, 9 - 20, 31 5 Symbol A0 - A17 WE CE2 VCC NC I/O1 - I/O8 GND CE1 OE Description Address Inputs Write Enable Chip Enable Power Supply No Connection Data Input/Outputs Ground Chip Enable Output Enable A0 - A17 Address Inputs I/O1 - I/O8 GND CE1 OE WE CE2 VCC Data Input/Outputs 6 Ground 8 Chip Enable Output Enable Write Enable Chip Enable Power Supply 9 21 - 23, 25 - 29 24 30 32 (August, 2001, Version 1.0) 2 AMIC Technology, Inc. LP62S2048-T Series Pin Description - CSP Symbol A0 - A17 WE OE CE1 CE2 Description Address Inputs Write Enable Output Enable Chip Enable Chip Enable Symbol NC I/O1 - I/O8 VCC GND -Description No Connection Data Input/Output Power Supply Ground -- Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 2.7 0 2.0 -0.3 Typ. 3.0 0 Max. 3.3 0 VCC + 0.3 +0.6 30 1 Unit V V V V pF - (August, 2001, Version 1.0) 3 AMIC Technology, Inc. LP62S2048-T Series Absolute Maximum Ratings* VCC to GND . . . . . . . . . . . . . . . . . . . . -0.5V to + 4.6V IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . -25°C to + 85°C Storage Temperature, Tstg . . . . .. . . . . -55°C to + 125°C Temperature Under Bias, Tbias . . . . . . -10°C to + 85°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol Parameter (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V, GND = 0V) LP62S2048-70LLT/10LLT Min. Max. 1 µA VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH II/O = 0mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1 MHZ, II/O = 0mA Unit Conditions LP62S2048-70LT/10LT Min. Max. 1 ILI Input Leakage Current - ILO Output Leakage Current Active Power Supply Current - 1 - 1 µA ICC - 3 - 3 mA ICC1 Dynamic Operating Current - 30 - 30 mA ICC2 - 5 - 5 mA (August, 2001, Version 1.0) 4 AMIC Technology, Inc. LP62S2048-T Series DC Electrical Characteristics (continued) Symbol Parameter LP62.


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