LP62S16256EU-55LLI

LP62S16256E-I Series 256K X 16 BIT LOW VOLTAGE CMOS SRAM Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Change VCCmax from 3.3V to 3.6V Add product family and 55ns specification Issue Date January 25, 2002 Remark (January, 2002, Version 2.0) AMIC Technology, Inc. LP62S16256E-I Series 256K X 16 BIT LOW VOLTAGE CMOS SRAM Features n Operating voltage: 2.7V to 3.6V n Access times: 55ns / 70ns (max.) n Current: Very low power version: Operating: 40mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2.0V (min.) n Available in 44-pin TSOP and 48-ball CSP (6 × 8mm) packages General Description The LP62S16256E-I is a low operating current 4,194,304-bit static random access memory organized as 262,144 words by 16 bits and operates on low power voltage from 2.7V to 3.3V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family Operating Temperature -40°C ~ +85°C VCC Range 2.7V~3.6V Speed Power Dissipation Data Retention Standb...