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LP62S1024A-T Dataheets PDF



Part Number LP62S1024A-T
Manufacturers AMIC Technology
Logo AMIC Technology
Description 128K X 8 BIT LOW VOLTAGE CMOS SRAM
Datasheet LP62S1024A-T DatasheetLP62S1024A-T Datasheet (PDF)

LP62S1024A-T Series 128K X 8 BIT LOW VOLTAGE CMOS SRAM Features n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating:(70NS)30mA(max.) (55NS)40mA(max.) Standby:5uA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin S.

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LP62S1024A-T Series 128K X 8 BIT LOW VOLTAGE CMOS SRAM Features n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating:(70NS)30mA(max.) (55NS)40mA(max.) Standby:5uA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) forward type and 36-pin CSP packages General Description The LP62S1024A-T is a low operating current 1,048,576bit static random access memory organized as 131,072 words by 8 bits and operates on a low power voltage: 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOP n TSOP/TSSOP n CSP (Chip Size Package) 36-pin Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 32 31 30 29 28 VCC A15 CE2 WE A13 A B C D E F G H 17 32 1 A0 I/O5 I/O6 GND VCC I/O7 I/O8 A9 OE A10 NC CE1 A11 NC A16 A12 A15 A13 2 A1 A2 3 CE2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O1 I/O2 VCC GND I/O3 I/O4 A14 16 1 LP62S1024AV-T (LP62S1024AX-T) LP62S1024AM-T 6 7 8 9 10 11 12 13 14 15 16 27 26 25 24 23 22 21 20 19 18 17 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 5 WE 21 I/O1 6 CE2 22 I/O 2 7 A15 23 I/O 3 8 VCC 24 GND 9 NC 25 I/O4 10 A16 26 I/O5 11 A14 27 I/O6 12 A12 28 I/O 7 13 A7 29 I/O 8 14 A6 30 CE1 15 A5 31 A10 16 A4 32 OE (August, 2001, Version 1.0) 1 AMIC Technology, Inc. LP62S1024A-T Series Block Diagram A0 VCC GND A14 A15 A16 ROW DECODER 512 X 2048 MEMORY ARRAY I/O1 INPUT DATA CIRCUIT COLUMN I/O I/O8 CE2 CE1 OE WE CONTROL CIRCUIT Pin Descriptions - SOP Pin No. 1 2 - 12, 23, 25 - 28, 31 13 - 15, 17 - 21 16 22 24 29 30 32 Symbol NC A0 - A16 Description No Connection Address Inputs Pin Description – TSOP/TSSOP Pin No. 1 - 4, 7, 10 - 20, 31 5 6 8 9 21 - 23, 25 - 29 24 30 32 Symbol A0 - A16 WE CE2 VCC NC I/O1 - I/O8 GND CE1 OE Description Address Inputs Write Enable Chip Enable Power Supply No Connection Data Input/Outputs Ground Chip Enable Output Enable I/O1 - I/O8 GND CE1 OE WE CE2 VCC Data Input/Outputs Ground Chip Enable Output Enable Write Enable Chip Enable Power Supply (August, 2001, Version 1.0) 2 AMIC Technology, Inc. LP62S1024A-T Series Pin Description - CSP Symbol A0 - A16 WE OE CE1 CE2 Description Address Inputs Write Enable Output Enable Chip Enable Chip Enable Symbol NC I/O1 - I/O8 VCC GND -Description No Connection Data Input/Output Power Supply Ground -- Recommended DC Operating Conditions (TA = -25°C to +85°C) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 2.7 0 2.0 -0.3 Typ. 3.0 0 Max. 3.6 0 VCC + 0.3 +0.6 30 1 Unit V V V V pF - (August, 2001, Version 1.0) 3 AMIC Technology, Inc. LP62S1024A-T Series Absolute Maximum Ratings* VCC to GND .............................................. -0.5V to +4.6V IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V Operating Temperature, Topr ................... -25°C to +85°C Storage Temperature, Tstg..................... -55°C to +125°C Temperature Under Bias, Tbias................ -10°C to +85°C Power Dissipation, PT ...............................................0.7W *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol Parameter (TA = -25°C to +85°C, VCC = 2.7V to 3.6V, GND = 0V) LP62S1024A-55LLT/70LLT Min. Max. 1 µA VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH II/O = 0mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1 MHZ, II/O = 0mA Unit Conditions ILI Input Leakage Current - ILO Output Leakage Current Active Power Supply Current - 1 µA ICC - 3 -70NS:30 mA ICC1 Dynamic Operating Current ICC2 5 -55NS:40 mA mA (August, 2001, Version 1.0) 4 AMIC Technology, Inc. LP62S1024A-T Series DC Electrical Characteristics (continued) Symbol Parameter LP62S1024A-55LLT/70LLT Min. ISB Max. 0.5 mA CE1 = VIH or CE2 =VIL CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V VIN ≥ 0V CE2 ≤ 0.


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