LP62P16128C-T

LP62P16128C-T Series Preliminary Document Title 128K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 128K X 16 BIT LOW VOLTAGE CMOS SRAM History Initial issue Issue Date March 11, 2002 Remark Preliminary PRELIMINARY (March, 2002, Version 0.0) AMIC Technology, Inc. LP62P16128C-T Series Preliminary Features n Operating voltage: 2.3V to 2.7V n Access times: 120 ns (max.) n Current: Very low power version: Operating: 20mA (max.) Standby: 100µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 1.2V (min.) n Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm) packages 128K X 16 BIT LOW VOLTAGE CMOS SRAM General Description The LP62P16128C-T is a low operating current 2,097,152-bit static random access memory organized as 131,072 words by 16 bits and operates on low power voltage from 2.3V to 2.7V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 1.2V. Pin Configurations n TSOP A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 1 2 3 4 44 43 42 41 A5 A6 A7 OE H...