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N04L63W2A
4Mb Ultra-Low Power Asynchronous CMOS SRAM
256K × 16 bit Overview
The N04L63W2A is an integrated memory device containing a 4 Mbit Static Random Access Memory organized as 262,144 words by 16 bits. The device is designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high-speed performance and ultra-low power. The device operates with two chip enable (CE1 and CE2) controls and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The N04L63W2A is optimal for various applications where low-power is critical such as battery backup and hand-held devices. The device can operate over a very wide temperature range of -40oC to +85oC and is available in JEDEC standard packages compatible with other standard 256Kb x 16 SRAMs
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Features
• Single Wide Power Supply Range 2.3 to 3.6 Volts • Very low standby current 4.0µA at 3.0V (Typical) • Very low operating current 2.0mA at 3.0V and 1µs (Typical) • Very low Page Mode operating current 0.8mA at 3.0V and 1µs (Typical) • Simple memory control Dual Chip Enables (CE1 and CE2) Output Enable (OE) for memory expansion • Low voltage data retention Vcc = 1.8V • Very fast output enable access time 25ns OE access time • Automatic power down to standby mode • TTL compatible three-state output driver • Compact space saving BGA package available
Product Family
Part Number N04L63W2AB N04L63W2AT N04L63W2AB2 N04L63W2AT2 Package Type 48 - BGA 44 - TSOP II 48 - BGA Green 44 - TSOP II Green 70ns @ 2.7V -40oC to +85oC 2.3V - 3.6V 55ns @ 2.7V 4 µA 2 mA @ 1MHz Operating Temperature Power Supply (Vcc) Speed Options Standby Operating Current (ISB), Current (Icc), Typical Typical
Pin Configuration
A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN ONE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CE2 A8 A9 A10 A11 A17
1 A B C D E F G H
LB I/O8 I/O9 VSS VCC
2
OE UB I/O10 I/O11 I/O12
3
A0 A3 A5 A17 NC A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11
6
CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC
Pin Descriptions
Pin Name A0-A17 WE CE1, CE2 OE LB UB I/O0-I/O15 VCC VSS NC Pin Function Address Inputs Write Enable Input Chip Enable Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs Power Ground Not Connected
N04L63W2A TSOP-II
I/O14 I/O13 I/O15 NC NC A8
48 Pin BGA (top) 6 x 8 mm
©2008 SCILLC. All rights reserved. July 2008 - Rev. 10
Publication Order Number: N04L63W2A/D
N04L63W2A
Functional Block Diagram
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Address Inputs A0 - A3
Word Address Decode Logic
Address Inputs A4 - A17
Page Address Decode Logic
16K Page x 16 word x 16 bit RAM Array
Input/ Output Mux a.