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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer's
TMOS E-FET .™ Power Field Effect Transistor DPAK for Surface Mount N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Surface Mount Package Available in 16 mm, 13–inch/2500 Unit Tape & Reel, Add –T4 Suffix to Part Number
™
Data Sheet
MTD6N20E
Motorola Preferred Device
TMOS POWER FET 6.0 AMPERES 200 VOLTS RDS(on) = 0.7 OHM
®
D
CASE 369A–13, Style 2 DPAK G S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Drain–to–Source Voltage Drain–to–Gate Voltage (RGS = 1.0 MΩ) Gate–to–Source Voltage — Continuous — Non–repetitive (tp ≤ 10 ms) Drain Current — Continuous — Continuous @ 100°C — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG = 25 Ω) Thermal Resistance — Junction to Case — Junction to Ambient — Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 200 200 ± 20 ± 40 6.0 3.8 18 50 0.4 1.75 – 55 to 150 54 2.50 100 71.4 260 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/°C Watts °C mJ °C/W
TJ, Tstg EAS RθJC RθJA RθJA TL
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
TMOS © Motorola Motorola, Inc. 1995
Power MOSFET Transistor Device Data
1
MTD6N20E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 µAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VD.