3.3 V ECL Programmable Delay Chip
MC100EP196B
3.3 V ECL Programmable Delay Chip With FTUNE
Descriptions
The MC100EP196B is a Programmable Delay Chip (PD...
Description
MC100EP196B
3.3 V ECL Programmable Delay Chip With FTUNE
Descriptions
The MC100EP196B is a Programmable Delay Chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tunability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from VCC to VEE to fine tune the output delay from 0 to 60 ps. The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP196B has a digitally selectable resolution of about
10 ps and a net range of up to 10.4 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(Pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any ...
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