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FS6377-01g Dataheets PDF



Part Number FS6377-01g
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Programmable 3-PLL Clock Generator
Datasheet FS6377-01g DatasheetFS6377-01g Datasheet (PDF)

FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 1.0 Features • Three on-chip PLLs with programmable reference and feedback dividers • Four independently programmable muxes and post dividers • I2C™-bus serial interface • Programmable power-down of all PLLs and output clock drivers Data Sheet www.DataSheet4U.com • One PLL and two mux/post-divider combinations can be modified by SEL_CD input • Tristate outputs for board testing • 5V to 3.3V operation • Accepts 5MHz to 27MHz crystal re.

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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 1.0 Features • Three on-chip PLLs with programmable reference and feedback dividers • Four independently programmable muxes and post dividers • I2C™-bus serial interface • Programmable power-down of all PLLs and output clock drivers Data Sheet www.DataSheet4U.com • One PLL and two mux/post-divider combinations can be modified by SEL_CD input • Tristate outputs for board testing • 5V to 3.3V operation • Accepts 5MHz to 27MHz crystal resonators • Commercial (FS6377-01) and industrial (FS6377-01i) temperature ranges 2.0 Description The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three I2C-programmable phaselocked loops feeding four programmable muxes and post dividers provide a high degree of flexibility. SDA SEL_CD PD VSS XIN XOUT OE VDD 1 2 3 16 15 14 SCL CLK_A VDD CLK_B CLK_C VSS CLK_D ADDR FS6377 4 5 6 7 8 13 12 11 10 9 16-pin (0.150") SOIC Figure 1: Pin Configuration XIN XOUT Reference Oscillator PLL A Mux A Post Divider A CLK_A PD Power Down Control PLL B Mux B Post Divider B CLK_B SCL SDA ADDR I2C-bus Interface PLL C Mux C Post Divider C CLK_C SEL_CD Mux D Post Divider D CLK_D OE FS6377 Figure 2: Block Diagram AMI Semiconductor www.amis.com 1 FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Table 1. Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type DIuO DI P AI AO DI P DI P DO DO P DO DIu u u u Data Sheet www.DataSheet4U.com Name SDA SEL_CD PD VSS XIN XOUT OE VDD ADDR CLK_D VSS CLK_C CLK_B VDD CLK_A SCL Description Serial interface data input/output Selects one of two PLL C, mux D/C and post divider C/D combinations Power-down input Ground Crystal oscillator input Crystal oscillator output Output enable input Power supply (5V to 3.3V) Address select D clock output Ground C clock output B clock output Power supply (5V to 3.3V) A clock output Serial interface clock input U DIu DO Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input With Internal Pull-Up; DID = Input With Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin 3.0 Functional Block Description 3.1 Phase Locked Loops Each of the three on-chip phase-locked loops (PLLs) is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), and a feedback divider. During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the reference divider. The divider value is called the "modulus," and is denoted as NR for the reference divider. The divided reference is then fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a highspeed, low noise, continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider (the modulus is denoted by NF) to close the loop. REFDIV[7:0] CP LFTC Loop Filter fREF Reference Divider (NR) PhaseFrequency Detector fPD UP Charge Pump DOWN FBKDIV[10:0] Voltage Controlled Oscillator fVCO Feedback Divider (NF) Figure 3: PLL Diagram The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frquency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is: f VCO = f REF ( ) NF NR . AMI Semiconductor www.amis.com 2 FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC 3.1.1 Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to the PFD. The reference divider is an 8-bit divider, and can be Data Sheet www.DataSheet4U.com programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h. 3.1.2 Feedback Divider The feedback divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider. For example, a fixed divide-by-eight could be used in th.


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