H5DU2582GTR

www.DataSheet4U.com 256Mb DDR SDRAM H5DU2562GTR H5DU2582GTR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Sep. 2009 1 www.DataSheet4U.com H5DU2562GTR H5DU2582GTR Revision History Revision No. 0.1 0.2 1.0 1.1 Preliminary Revised tRC, tWR spec @ DDR500 Release Revised Operating Frequency History Draft Date Jun. 2009 Jun. 2009 Jul. 2009 Sep. 2009 Remark Rev. 1.1 / Sep. 2009 2 www.DataSheet4U.com H5DU2562GTR H5DU2582GTR DESCRIPTION The H5DU2582GTR and H5DU2562GTR are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source sy...