56F8025

www.DataSheet4U.com 56F8035/56F8025 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8025 Rev. 6 02/2010 freescale.com www.DataSheet4U.com Document Revision History Version History Rev. 0 Rev. 1 Initial public release. In Table 5-3, changed the ITCN_BASE address from $00 F060 (incorrect value) to $00 F0E0 (the correct value). In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz. Changed input propagation delay values in Table 10-20 as follows: Old values: 1 μs typical, 2 μs maximum New values: 35 ns typical, 45 ns maximum Rev. 2 In Table 10-19, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz. Replaced the case outline schematics in Figure 11-2, Figure 11-3, and Figure 11-4. Rev. 3 Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor. Changed the VBA register reset value and updated the footnote in Section 5.6.8. Changed the STANDBY > STOP IDD values in Table 10-6 as follows: Typical: was 290μA, is 540μA Maximum: was 390μA, is 650μA Changed the POWERDOWN IDD values in Table 10-6 as follows: Typical: was 190μA, is 440μA Maximum: was 250μA, is 550μA Changed footnote 1 in Table...