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PMGD400UN
Dual N-channel µTrenchMOS™ ultra low level FET
MBD128
Rev. 01 — 3 March 2004
Product data
1. Product profile
1.1 Description
Dual N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology.
1.2 Features
s Surface mounted package s Dual device s Low on-state resistance s Footprint 40% smaller than SOT23 s Fast switching s Low threshold voltage.
1.3 Applications
s Driver circuits s Switching in portable appliances.
1.4 Quick reference data
s VDS ≤ 30 V s Ptot ≤ 0.41 W s ID ≤ 0.71 A s RDSon ≤ 480 mΩ.
2. Pinning information
Table 1: Pin 1 2 3 4 5 6 Pinning - SOT363 (SC-88), simplified outline and symbol Description source (s1) gate (g1) drain (d2) source (s2) gate (g2) drain (d1)
s1 1 Top view 2 3
MSA370
Simplified outline
6 5 4
Symbol
d1 d2
g1
s2
g2
MSD901
SOT363 (SC-88)
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Philips Semiconductors
PMGD400UN
Dual N-channel µTrenchMOS™ ultra low level FET
3. Ordering information
Table 2: Ordering information Package Name PMGD400UN SC-88 Description Plastic surface mounted package; 6 leads Version SOT363 Type number
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM
[1]
Conditions 25 °C ≤ Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ Tsp = 25 °C; VGS = 4.5 V; Figure 2 and 3 Tsp = 100 °C; VGS = 4.5 V; Figure 2 Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tsp = 25 °C; Figure 1
[1] [1] [1]
Min −55 −55
[1] [1]
Max 30 30 ±8 0.71 0.45 1.42 0.41 +150 +150 0.34 0.69
Unit V V V A A A W °C °C A A
drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature
Source-drain diode source (diode forward) current (DC) Tsp = 25 °C peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs
Single device conducting.
-
9397 750 12759
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 3 March 2004
2 of 12
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Philips Semiconductors
PMGD400UN
Dual N-channel µTrenchMOS™ ultra low level FET
120 Pder (%) 80
03aa17
120 Ider (%) 80
03aa25
40
40
0 0 50 100 150 Tsp (°C) 200
0 0 50 100 150 200 Tsp (°C)
P tot P der = ---------------------- × 100 % P °
tot ( 25 C )
ID I der = ------------------- × 100 % I °
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of solder point temperature.
Fig 2. Normalized continuous drain current as a function of solder point temperature.
10
03an21
ID (A)
Limit RDSon = VDS / ID tp = 10 µ s 1 100 µ s
10-1
DC
1 ms 10 ms
100 ms
10-2 10-1 1 10 VDS (V) 102
Tsp = 25 °C; IDM is single pulse; VGS = 4.5 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12759
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 3 March 2004
3 of 12
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Philips Semiconductors
PMGD400UN
Dual N-channel µTrenchMOS™ ultra low level FET
5. Thermal characteristics
Table 4: Rth(j-sp) Thermal characteristics Conditions Min Typ Max 300 Unit K/W thermal resistance from junction to solder point Figure 4 Symbol Parameter
5.1 Transient thermal impedance
103 Zth(j-sp) (K/W) δ = 0.5 102 0.2 0.1 0.05 0.02 10 single pulse P
03an28
δ=
tp T
tp T 1 10-4 10-3 10-2 10-1 1
t
tp (s)
10
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 12759
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 3 March 2004
4 of 12
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Philips Semiconductors
PMGD400UN
Dual N-channel µTrenchMOS™ ultra low level FET
6. Characteristics
Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 1 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 0.25 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 150 °C Tj = −55 °C IDSS drain-source leakage current VDS = 30 V; VGS = 0 V Tj = 25 °C Tj = 150 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±8 V; VDS = 0 V VGS = 4.5 V; ID = 0.2 A; Figure 7 and 8 Tj = 25 °C Tj = 150 °C VGS = 2.5 V; ID = 0.1 A; Figure 7 and 8 VGS = 1.8 V; ID = 0.075 A; Figure 7 and 8 Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 0.3 A; VGS = 0 V; Figure 12 VDD = 15 V; RL = 15 Ω; VGS = 4.5 V; RG = 6 Ω VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 ID = 1 A; VDD = 15 V; VGS = 4.5 V; Figure 13 0.89 0.1 0.2 43 7.7 4.8 4 7.5 18 4.5 0.76 1.2 nC nC nC pF pF pF ns ns ns ns V 400 660 480 580 480 816 .