IDT72P51769

1.8V MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits 4,718,592 bits ADVANCE INFORMATION www.DataSheet4U.com IDT72P51749 IDT72P51759 IDT72P51769 FEATURES Choose from among the following memory density options: IDT72P51749  Total Available Memory = 1,179,648 bits IDT72P51759  Total Available Memory = 2,359,296 bits IDT72P51769  Total Available Memory = 4,718,592 bits Configurable from 1 to 128 Queues Default configuration of 128 or 64 symmetrical queues Default multi-queue device configurations – IDT72P51749: 256 x 36 x 128Q – IDT72P51759: 512 x 36 x 128Q – IDT72P51769: 1,024 x 36 x 128Q Default configuration can be augmented via the queue address bus Number of queues and individual queue sizes may be configured at master reset though serial programming 200 MHz High speed operation (5ns cycle time) 3.6ns access time Independent Read and Write access per queue User Selectable Bus Matching Options: – x36 in to x36 out – x18 in to x36 out – x9 in to x36 out – x36in to x18out – x18 in to x18 out – x9 in to x18 out – x36in to x9out – x18 in to x9 out – x9 in to x9 out User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL 100% Bus Utilization, Read and Write on every clock cycle Selectable First Word Fall Through (FWFT) or IDT standard mode of operation Ability to operate on packet or word boundaries Mark and Re-Write operation Mark and Re-Read operation Individual, A...