Multiphase, Fixed-Frequency Controller forwww.DataSheet4U.com
AMD Hammer CPU Core Power Supplies
Low-Voltage VID DAC Code Input. The D0–D4 inputs do not have internal pullups. These 1.0V logic inputs
are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the output voltage
is set by the VID code indicated by the logic-level voltages on D0–D4. In suspend mode (SUS = high), the
output voltage tracks the voltage at SUSV.
2 D3 Low-Voltage VID DAC Code Input
3 D4 Low-Voltage VID DAC Code Input (MSB)
4 N.C. No Connect. Leave open. Pin internally connected.
Pulse-Skipping Indicator Input. When pulse skipping, the controller blanks the VROK upper threshold.
3.3V or VCC (high) = 1-phase pulse-skipping operation (phases 2, 3, and 4 disabled)
GND = multiphase forced-PWM operation
The controller automatically enters forced-PWM mode during startup, shutdown, and the no-CPU VID
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal
operation. Connect to ground to put the IC into its 50nA (typ) shutdown state. During the startup and
shutdown transitions, the output voltage is ramped at 1/4th the output-voltage slew rate programmed by
RTIME. After completing soft-shutdown, the drivers are disabled—DRSKP and PWM_ are pulled low.
Forcing SHDN to 11V~13V disables both overvoltage-protection and undervoltage-protection circuits, and
clears the fault latch. Do not connect SHDN to >13V.
Suspend Control Input. When the controller detects a transition on SUS, the controller slews the output
voltage to the new voltage level determined by SUSV (SUS = high) or D0–D4 (SUS = low). The controller
blanks VROK during the transition and another 20µs after the new target voltage is reached. When SUS is
high, the offset (OFS) is automatically disabled.
Suspend-Mode Voltage Input. Connect to the output of a resistive voltage-divider from REF to GND to
8 SUSV provide an analog voltage between 0.4V to 2V. The output voltage is set by the voltage at SUSV when SUS
Average Current-Limit Threshold Adjustment. The controller uses the accurate CRSP-to-CRSN current-
sense voltage to limit the average current per phase. When the average current-limit threshold is
exceeded, the controller internally reduces the peak inductor current-limit threshold (ILIM(PK)) at 2% of
IPKLIMIT per µs until the average current remains within the programmed limits. When the accurate current
sensing is disabled (CRSP = VCC), the average current-limit circuit is disabled and ILIM(AVE) should be
connected to VCC.
The average current-limit threshold defaults to 25mV if ILIM(AVE) is connected to VCC. In adjustable mode,
the average current-limit threshold voltage is precisely 1/20th the voltage difference between ILIM(AVE)
and the reference: (VREF - VILIM(AVE)) / 20 for a range of 1.0V (VREF - 1V) to 1.8V (VREF - 0.2V). The logic
threshold for switchover to the 25mV default value is approximately VCC - 1V.
Adjustable Offset Voltage Input. For 0 < VOFS < 0.8V, 1/8th the voltage at OFS is subtracted from the
output. For 1.2V < VOFS < 2.0V, 1/8th the difference between REF and OFS is added to the output.
Voltages in the range of 0.8V < VOFS < 1.2V are undefined. The controller disables the offset amplifier
during suspend mode (SUS = high).