ZSP540

ZSP540 - Highly Efficient Quad-MAC DSP Core www.DataSheet4U.com O V E RV I E W The ZSP540 processor core is a high-performance/power-efficient QuadMAC/Six-ALU implementation of the ZSP® G2 architecture. The ZSP540 utilizes a 16-bit architecture with extensive 32-bit capabilities and sets an unmatched balance of performance/power/size and memory utilization efficiency. The Z.Turbo feature provides the SOC designer with the option to extend the ZSP540 Instruction Set and the ability to add application-specific acceleration logic. C O R E F E AT U R E S Quad-MAC/Six-ALU DSP core 4+1 instructions per cycle Up to 350MHz, 8-stage pipeline design Up to 1750 million instructions/sec Dual 64-bit wide Load/Store data ports Z.Turbo coprocessor extensions capable TARGET MARKETS 2.5/3G wireless baseband processing Multimedia wireless and mobile devices Cable/xDSL Wireless LAN (WLAN) Set-top box and home gateways Multi-channel Voice Over IP (VoIP) Software Defined Radio (SDR) 24-bit address space HW managed instructions scheduling HW/SW controlled power management Real-time trace and profiling capability Full AMBA/AHB support (optional) JTAG debug interface Static, single phase clocked design Compatible with all other ZSP cores A P P L I C AT I O N B E N E F I T S High-performance DSP capabilities Excellent power/cost/speed balance Excellent multimedia audio/video processing Power efficient baseband processing performance DSP and sy...