Document
ADC0804S030/040/050
Rev. 02 — 14 August 2008
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Product data sheet
1. General description
The ADC0806030/040/050 are a family of 8-bit high-speed, low-power Analog-to-Digital Converters (ADC) for professional video and other applications. It converts the analog input signal into 8-bit binary coded digital signals at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal can also be used. The device requires an external source to drive its reference ladder. If the application requires that the reference is driven via internal sources, NXP recommends you use one of the ADC1003S030/040/050 family.
2. Features
I I I I I I I I I I I I I I 8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) No missing codes guaranteed In-Range (IR) CMOS output TTL and CMOS levels compatible digital inputs 3 V to 5 V CMOS digital outputs Low-level AC clock input signal allowed External reference voltage regulator Power dissipation only 175 mW (typical) Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required
3. Applications
I I I I I I I Video data digitizing Radar Transient signal analysis Σ∆ modulators Medical imaging Barcode scanner Global Positioning System (GPS) receiver
NXP Semiconductors
ADC0804S030/040/050
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
www.DataSheet4U.com
I Cellular base stations
4. Quick reference data
Table 1. Quick reference data VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. Symbol VCCA VCCD VCCO ICCA ICCD ICCO INL DNL fclk(max) Parameter analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current integral non-linearity differential non-linearity maximum clock frequency fclk = 40 MHz; ramp input fclk = 40 MHz ramp input fclk = 40 MHz ramp input ADC0804S030TS ADC0804S040TS ADC0804S050TS Ptot total power dissipation fclk = 40 MHz; ramp input Conditions Min 4.75 4.75 3.0 30 40 50 Typ 5.0 5.0 3.3 18 16 1 ±0.2 ±0.12 175 Max 5.25 5.25 5.25 24 21 2 ±0.5 ±0.22 247 Unit V V V mA mA mA LSB LSB MHz MHz MHz mW
5. Ordering information
Table 2. Ordering information Package Name ADC0804S030TS ADC0804S040TS ADC0804S050TS SSOP28 SSOP28 SSOP28 Description plastic shrink small outline package; 28 leads; body width 5.3 mm plastic shrink small outline package; 28 leads; body width 5.3 mm plastic shrink small outline package; 28 leads; body width 5.3 mm Version Sampling frequency (MHz) Type number
SOT341-1 30 SOT341-1 40 SOT341-1 50
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
2 of 19
NXP Semiconductors
ADC0804S030/040/050
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
www.DataSheet4U.com
6. Block diagram
VCCA 3
CLK 1
VCCD2 11
OE 10
CLOCK DRIVER RT 9
2
TC
25 D7 24 D6 Rlad analog voltage input VI 8 ANALOG - TO - DIGITAL CONVERTER LATCHES CMOS OUTPUTS 23 D5 22 D4 21 D3 20 D2 RM 7 19 D1 18 D0
MSB
data outputs
LSB
RB
6
13
VCCO
ADC0804S030
IN-RANGE LATCH
CMOS OUTPUT
26
IR output
28 4 AGND analog ground 12 DGND2 digital ground 14 OGND output ground 27 DGND1
VCCD1
digital ground
014aaa550
Fig 1. Block diagram
ADC0804S030_040_050_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
3 of 19
NXP Semiconductors
ADC0804S030/040/050
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
www.DataSheet4U.com
7. Pinning information
7.1 Pinning
CLK TC VCCA AGND n.c. RB RM VI RT
1 2 3 4 5 6 7 8 9
28 VCCD1 27 DGND1 26 IR 25 D7 24 D6 23 D5 22 D4 21 D3 20 D2 19 D1 18 D0 17 n.c. 16 n.c. 15 n.c.
014aaa551
ADC0804S 030TS
OE 10 VCCD2 11 DGND2 12 VCCO 13 OGND 14
Fig 2.
Pin configuration
7.2 Pin description
Table 3. Symbol CLK TC VCCA AGND n.c. RB RM VI RT OE VCCD2 DGND2 VCCO OGND n.c. n.c. n.c. D0 D1 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description clock input two’s complement input (active LOW) analog supply voltage (5 V) analog ground not connected reference voltage BOTTOM input reference voltage MIDDLE analog input voltage reference voltage TOP input output enable input (CMOS level input, active LOW) digital supply voltage 2 (5 V) digital ground 2 supply voltage for output stages (3 V to 5 V) output ground not connected not connected not connected data output; bit 0 (Least Significant Bit (LSB)) data output; bit 1
ADC0804S030_040_.