Document
ADC0801S040
Single 8 bits ADC, up to 40 MHz
Rev. 03 — 2 July 2012
Product data sheet
1. General description
The ADC0801S040 is an 8-bit universal analog-to-digital converter (ADC) for video and general purpose applications. It converts the analog input signal from 2.7 V to 5.5 V into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are CMOS/Transistor-Transistor Logic (TTL) compatible. A sleep mode allows reduction of the device power consumption to 4 mW.
2. Features
8-bit resolution Operation between 2.7 V and 5.5 V Sampling rate up to 40 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits
at 4.43 MHz full-scale input at fclk = 40 MHz) CMOS/TTL compatible digital inputs and outputs External reference voltage regulator Power dissipation only 30 mW (typical value) Low analog input capacitance, no buffer amplifier required Sleep mode (4 mW) No sample-and-hold circuit required
3. Applications
Video data digitizing Camera Camcorder Radio communication Car alarm system
®
Integrated Device Technology
ADC0801S040
Single 8 bits ADC, up to 40 MHz
4. Quick reference data
Table 1. Quick reference data
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(a)(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified.
Symbol Parameter Conditions
Min Typ Max Unit
VDDA
analog supply voltage
2.7
3.3
5.5
V
VDDD
digital supply voltage
2.7
3.3
5.5
V
VDDO
output supply voltage
2.5
3.3
5.5
V
VDD IDDA
supply voltage difference
analog supply current
VDDA VDDD VDDD VDDO
0.2 -
0.2 -
-
4
+0.2 V
+2.25 V
6
mA
IDDD
digital supply
current
-
5
8
mA
IDDO INL
output supply current
integral non-linearity
fclk = 40 MHz; ramp input; CL = 20 pF ramp input; see Figure 6
-
1
2
mA
-
0.5 0.75 LSB
DNL
differential non-linearity
ramp input; see Figure 7
-
0.25 0.5 LSB
fclk(max)
maximum clock frequency
40
-
-
MHz
Ptot
total power
VDDA = VDDD = VDDO = 3.3 V
-
30
53
mW
dissipation
5. Ordering information
Table 2. Ordering information
Type number
Package
Name
ADC0801S040TS
SSOP20
Description plastic shrink small outline package; 20 leads; body width 4.4 mm
Version SOT266-1
3ADC0801S040_3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
2 of 18
Integrated Device Technology
6. Block diagram
ADC0801S040
Single 8 bits ADC, up to 40 MHz
VDDA 5
CLK 1
VDDD 3
RT 10
CLOCK DRIVER
ADC0801S040
2 SLEEP
analog VI 9 voltage input
RM 8
Rlad
ANALOG - TO - DIGITAL CONVERTER
LATCHES
RB 7
CMOS OUTPUTS
19 D7 18 D6 17 D5 16 D4 15 D3 14 D2 13 D1 12 D0
MSB data outputs LSB
20
VDDO
6 VSSA analog ground
Fig 1. Block diagram
11 VSSO
4 VSSD
output ground digital ground
014aaa495
3ADC0801S040_3
Product data sheet
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