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K7P321874C Dataheets PDF



Part Number K7P321874C
Manufacturers Samsung Electronics
Logo Samsung Electronics
Description 1Mx36 & 2Mx18 SRAM
Datasheet K7P321874C DatasheetK7P321874C Datasheet (PDF)

K7P323674C K7P321874C Preliminary www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM 32Mb C-die LW SRAM Specification 119BGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON .

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K7P323674C K7P321874C Preliminary www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM 32Mb C-die LW SRAM Specification 119BGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. -1- Jan. 2005 Rev 0.1 K7P323674C K7P321874C Document Title 1Mx36 & 2Mx18 Synchronous Pipelined SRAM Preliminary www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM Revision History Rev. No. Rev. 0.0 Rev. 0.1 History - Initial Document - Change VDD range : from 1.8~2.5V to 1.8 or 2.5V Draft Date Dec. 2005 Jan. 2005 Remark Preliminary Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters. -2- Jan. 2005 Rev 0.1 K7P323674C K7P321874C 1Mx36 & 2Mx18 Synchronous Pipelined SRAM FEATURES • 1Mx36 or 2Mx18 Organizations. • 1.8 or 2.5V VDD/1.5V ~1.8VDDQ. • HSTL Input and Output Levels. • Differential, HSTL Clock Inputs K, K. • Synchronous Read and Write Operation • Registered Input and Registered Output • Internal Pipeline Latches to Support Late Write. Preliminary www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM • Byte Write Capability(four byte write selects, one for each 9bits) • Synchronous or Asynchronous Output Enable. • Power Down Mode via ZZ Signal. • Programmable Impedance Output Drivers. • JTAG 1149.1 Compatible Test Access port. • 119(7x17)Pin Ball Grid Array Package(14mmx22mm). GENERAL DESCRIPTION The K7P323674C and K7P321874C are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of 36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology. Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch. ORDERING INFORMATION Org. 1Mx36 2Mx18 Maximum Frequency 300MHz 250MHz 300MHz 250MHz Access Time 1.6 2.0 1.6 2.0 VDD 2.5V 1.8 / 2.5V 2.5V 1.8 / 2.5V Part Number K7P323674C-H(G)C30 K7P323674C-H(G)C25 K7P321874C-H(G)C30 K7P321874C-H(G)C25 Note 1 : 300MHz is supported only at 2.5V VDD. 250MHz is the maximum speed at 1.8V VDD 2 : G in the part number means Lead free package. -3- Jan. 2005 Rev 0.1 K7P323674C K7P321874C FUNCTIONAL BLOCK DIAGRAM SA[0:19] or SA[0:20] CK SS SW Latch SWx Register SWx Register Latch SW Register SW Register Read Address Register Preliminary www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM Row Decoder 1 Write Address Register 0 1Mx36 or 2Mx18 Array Column Decoder Write/Read Circuit SWx (x=a, b, c, d) or (x=a, b) 0 1 Data In Register SS Register SS Register Data Out Register G ZZ K K CK DQx[1:9] (x=a, b, c, d) or (x=a, b) PIN DESCRIPTION Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD VDDQ Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asynchronous Power Down Core Power Supply Output Power Supply Pin Name VREF M 1 , M2 G SS TCK TMS TDI TDO ZQ VSS NC Pin Description HSTL Input Reference Voltage Read Protocol Mode Pins ( M1=VSS, M2=VDDQ ) Asynchronous Output Enable Synchronous Select JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output Output Driver Impedance Control GND No Connection -4- Jan. 2005 Rev 0.1 K7P323674C K7P321874C PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7P323674C(1Mx36) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQ.


KFG1G16Q2A-DEBx K7P321874C K7P323674C


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