Document
White Electronic Designs
W78M64V-XSBX
www.DataSheet4U.com
8Mx64 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package
FEATURES
Access Times of 70, 90, 100, 120ns Packaging • 159 PBGA, 13x22mm – 1.27mm pitch 1,000,000 Erase/Program Cycles per sector Page Mode • Page size is 8 words: Fast page read access from random locations within the page. Sector Architecture • Bank A (16Mb): 4Kw x 8 and 32 Kw x 31 • Bank B (48Mb): 32Kw x 96 • Bank C (48Mb): 32Kw x 96 • Bank D (16Mb): 4Kw x 8 and 3Kw x 31 Both top and bottom boot blocks Zero Power Operation Organized as 8Mx64, user configurable as 2x8Mx32 or 4x8Mx16 Commercial, Industrial and Military Temperature Ranges 3.3 Volt for read, erase and write operations Simultaneous read/write operations: • Data can be continuously read from one bank while executing erase/program functions in another bank • Zero latency between read and write operations Erase Suspend/Resume • Suspends erase operations to allow read or programming in other sectors of same bank Data Polling and Toggle Bits • Provides a software method of detecting the status of program or erase cycles
* This product is subject to change without notice.
Unlock Bypass Program command • Reduces overall programming time when issuing multiple program command sequences Ready/Busy# output (RY/BY#) • Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) • Hardware method of resetting the internal state machine to the read mode WP#/ACC input pin • Write protect (WP#) function allows protection of two outermost boot sector, regardless of sector protect status • Acceleration (ACC) function accelerates program timing Persistent Sector Protection • A command sector protection method of locking combinations of individual sectors and sector groups to prevent program or erase operation within that sector Password Sector Protection or Cancellation • A sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 3 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIG 1: PIN CONFIGURATION FOR W78M64V-XSBX (TOP VIEW)
W78M64V-XSBX
www.DataSheet4U.com
1 A B C D E F G H J K L M N P R T
VIO
2
GND
3
GND
4
GND
5
VCC
6
VIO
7
GND
8
GND
9 10
GND VCC
PIN DESCRIPTION
DQ0-63 A0-22 WE#1-4 CS#1-4 OE# RESET# WP#/ACC RY/BY# VCC VIO GND DNU Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Hardware Reset Hardware Write Protection/Acceleration Ready/Busy Output Power Supply I/O Power Supply Ground Do Not Use
GND
DQ41
WE3#
VIO
DQ57
DNU
WE4#
VCC
VIO
VCC
DQ33
DQ43
DQ45
DQ47
DQ49
DQ59
DQ61
DQ63
VCC
VIO
DQ40
DQ35
DQ37
DQ39
DQ56
DQ51
DQ53
DQ55
VIO
VCC
DQ32
DQ42
DQ44
DQ46
DQ48
DQ58
DQ60
DQ62
VCC
GND
CS3#
DQ34
DQ36
DQ38
CS4#
DQ50
DQ52
DQ54
GND
GND
OE#
A0
A22
VCC
A12
A16
A21
A20
GND
GND
A2
WP#/ACC
A11
GND
VIO
A7
A10
A15
GND*
GND
A3
A6
A9
VCC
GND
A1
RESET#
A13
GND
GND
A4
A17
RY/BY#
GND
A14
A5
A18
A8
GND
BLOCK DIAGRAM
GND DQ17 WE2# DQ29 DNU* DQ9 DQ4 WE1# A19 GND VIO DQ24 DQ19 DQ21 DQ31 DQ1 DQ11 DQ6 DQ15 VIO
WE1# WE2# CS2# WE3# CS3# WE4# CS4# CS1# RY/BY# RESET# OE# A0-22
VCC
DQ16
DQ26
DQ28
DQ23
DQ8
DQ3
DQ13
DQ7
VCC
VIO
CS2#
DQ18
DQ20
DQ30
DQ0
DQ10
DQ5
DQ14
VIO
VCC
VCC
DQ25
DQ27
DQ22
CS1#
DQ2
DQ12
GND
VCC
8M X 16
8M X 16
8M X 16
8M X 16
VIO
GND
GND
GND
VIO
VCC
GND
GND
GND
VIO
WP#/ACC
* Ball L5 is reserved for A23 for future upgrades.
DQ0-15
DQ16-31
DQ32-47
DQ48-63
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 3 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
GENERAL DESCRIPTION
The W78M64V-XSBX is a 512Mb, 3.3 volt-only Page Mode and Simultaneous Read/Write Flash memory device. The device offers fast page access times allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CS#), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving sys.