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MPC7410 Dataheets PDF



Part Number MPC7410
Manufacturers Freescale Semiconductor
Logo Freescale Semiconductor
Description RISC Microprocessor
Datasheet MPC7410 DatasheetMPC7410 Datasheet (PDF)

Freescale Semiconductor Technical Data MPC7410EC Rev. 6.1, 11/2007 MPC7410 RISC Microprocessor Hardware Specifications www.DataSheet4U.com The MPC7410 is a PowerPC™ reduced instruction set computing (RISC) microprocessor. This document describes pertinent electrical and physical characteristics of the MPC7410. For functional characteristics of the processor, refer to the MPC7410 RISC Microprocessor User’s Manual. To locate any published errata or updates for this document, refer to the web si.

  MPC7410   MPC7410



Document
Freescale Semiconductor Technical Data MPC7410EC Rev. 6.1, 11/2007 MPC7410 RISC Microprocessor Hardware Specifications www.DataSheet4U.com The MPC7410 is a PowerPC™ reduced instruction set computing (RISC) microprocessor. This document describes pertinent electrical and physical characteristics of the MPC7410. For functional characteristics of the processor, refer to the MPC7410 RISC Microprocessor User’s Manual. To locate any published errata or updates for this document, refer to the web site at http://www.freescale.com. 1 Overview 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical and Thermal Characteristics . . . . . . . . . . . . 7 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 29 System Design Information . . . . . . . . . . . . . . . . . . . 34 Document Revision History . . . . . . . . . . . . . . . . . . . 48 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 53 The MPC7410 is the second implementation of the fourth generation (G4) microprocessors from Freescale. The MPC7410 implements the full PowerPC 32-bit architecture and is targeted at both computing and embedded systems applications. Some comments on the MPC7410 with respect to the MPC750: • • The MPC7410 adds an implementation of the new AltiVec™ technology instruction set. The MPC7410 includes significant improvements in memory subsystem (MSS) bandwidth and offers an optional, high-bandwidth MPX bus interface. The MPC7410 adds full hardware-based multiprocessing capability, including a five-state cache coherency protocol (four MESI states plus a fifth state for shared intervention). • © Freescale Semiconductor, Inc., 2005, 2007. All rights reserved. Features • • • • The MPC7410 is implemented in a next generation process technology for core frequency improvement. The MPC7410 floating-point unit has been improved to make latency equal for double- and single-precision operations involving multiplication. The completion queue has been extended to eight slots. There are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms, or the branch unit. The MPC750 four-stage pipeline model is unchanged (fetch, decode/dispatch, execute, complete/writeback). The MPC7410 adds configurable direct-mapped SRAM capability to the L2 cache interface. The MPC7410 adds 32-bit interface support to the L2 cache interface. The MPC7410 implements a 19th L2 address pin (L2ASPARE on the MPC7400) in order to support additional address range. The MPC7410 removes support for 3.3-V I/O on the L2 cache interface. Some comments on the MPC7410 with respect to the MPC7400: • • • www.DataSheet4U.com Figure 1 shows a block diagram of the MPC7410. 2 • Features Branch processing unit — Four instructions fetched per clock — One branch processed per cycle (plus resolving two speculations) — Up to one speculative stream in execution, one additional speculative stream in fetch — 512-entry branch history table (BHT) for dynamic prediction — 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay slots Dispatch unit — Full hardware detection of dependencies (resolved in the execution units) — Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU) — Serialization control (predispatch, postdispatch, execution serialization) This section summarizes features of the MPC7410 implementation of the PowerPC architecture. Major features of the MPC7410 are as follows: • MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1 2 Freescale Semiconductor Instruction Unit 128-Bit (4 Instructions) Fetcher BTIC (64-Entry) 128-Entry ITLB Data MMU EA SRs (Original) DBAT Array 128-Entry DTLB Dispatch Unit PA 64-Bit (2 Instructions) 32-Kbyte Tags D Cache LR CTR BHT (512-Entry) IBAT Array Tags Branch Processing Unit SRs (Shadow) www.DataSheet4U.com Instruction MMU 32-Kbyte I Cache Freescale Semiconductor Instruction Queue (6-Word) Reservation Station VR File 6 Rename Buffers Integer Unit 1 Integer Unit 2 System Register Unit 6 Rename Buffers GPR File Reservation Station Reservation Station Reservation Station Reservation Station (2-Entry) FPR File 6 Rename Buffers Load/Store Unit + (EA Calculation) Load Fold 32-Bit Finished Queue Stores Reservation Station Vector ALU FloatingPoint Unit • • • • • • Additional Features Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor 2 Instructions Reservation Station Vec.


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