QL3060

QL3060 pASIC 3 FPGA Data Sheet 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density 60,000 Usable PLD Gates with 316 I/Os 300 MHz 16-bit www.DataSheet4U.com Eight Low-Skew Distributed Networks Two array clock/control networks available Counters, 400 MHz Datapaths 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use / Fast Development Cycles 100% routable with 100% utilization and to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin Six global clock/control networks available to the logic cell F1, clock set, and reset inputs and the input and I/O register clock, reset, and enable inputs as well as the output enable control — each driven by an inputonly or I/O pin, or any logic cell output or I/O cell feedback complete pin-out stability Variable-grain logic cells provide high performance and 100% utilization Comprehensive design tools include high quality Verilog/VHDL synthesis High Performance Input + logic cell + output total delays under 6 ns Data path speeds over 400 MHz Counter speeds over 300 MHz Advanced I/O Capabilities Interfaces with both 3.3 V and 5.0 V devices PCI compliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades Full JTAG boundary scan I/O Cells with individually controlled Registered Input Path and Output Enables Total of 316 I/O Pins 308 bidirectional i...