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K4X1G163PC-FE Dataheets PDF



Part Number K4X1G163PC-FE
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description Mobile DDR SDRAM
Datasheet K4X1G163PC-FE DatasheetK4X1G163PC-FE Datasheet (PDF)

K4X1G163PC - L(F)E/G 64Mx16 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( F.

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K4X1G163PC - L(F)E/G 64Mx16 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 ) • Internal Temperature Compensated Self Refresh • All inputs except data & DM are sampled at the positive going edge of the system clock(CK). www.DataSheet4U.com • Data I/O transactions on both edges of data strobe, DM for masking. • Edge aligned data output, center aligned data input. • No DLL; CK to DQS is not synchronized. • LMD, UMD for write masking only. • Auto refresh duty cycle - 7.8us for -25 to 85 °C Mobile DDR SDRAM 2. Operating Frequency DDR333 Speed @CL2 Speed @CL3 NOTE: 1) CAS Latency 1) 1) DDR266 83Mhz 133Mhz 83Mhz 166Mhz 3. Address configuration Organization 64Mx16 - DM is internally loaded to match DQ and DQS identically. Bank Address BA0,BA1 Row Address A0 - A13 Column Address A0 - A9 4. Ordering Information Part No. K4X1G163PC-L(F)E/GC6 K4X1G163PC-L(F)E/GC3 Max Freq. 166MHz(CL=3),83MHz(CL=2) 133MHz(CL=3),83MHz(CL=2) Interface LVCMOS Package 60FBGA Pb (Pb Free) - L(F)E : 60FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C) - L(F)G : 60FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C) - C6/C3 : 166MHz(CL=3) / 133MHz(CL=3) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. -4- November 2007 K4X1G163PC - L(F)E/G 5. FUNCTIONAL BLOCK DIAGRAM Mobile DDR SDRAM 16 LWE LDM I/O Control CK, CK Data Input Register Serial to parallel Bank Select 32 16Mx16 Output Buffer 2-bit prefetch www.DataSheet4U.com Sense AMP Refresh Counter Row Buffer Row Decoder 16Mx16 16Mx16 16Mx16 32 16 X16 DQi Address Register CK, CK ADD Column Decoder LCBR LRAS Col. Buffer Latency & Burst Length Strobe Gen. Data Strobe LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDM Timing Register DM Input Register C.


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