Document
K7P323666M K7P321866M
www.DataSheet4U.com
1Mx36 & 2Mx18 SRAM
32Mb M-die LW SRAM Specification
119BGA with Pb & Pb-Free
(RoHS compliant)
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* Samsung Electronics reserves the right to change products or specification without notice.
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Dec. 2005 Rev 1.2
K7P323666M K7P321866M
Document Title
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
www.DataSheet4U.com
1Mx36 & 2Mx18 SRAM
Revision History
Rev. No.
Rev. 0.0 Rev. 0.1
History
- Initial Document - x18 Organization Package Pin Configuration corrected(2T,4T, 6T) JTAG Instruction Coding 101 changed from Bypass to Private - Absolute maximum ratings are changed VDD : 2.815 - > 3.13 - Recommended DC operating conditions are changed VREF / VCM-CLK : 0.68 - > 0.6, 0.95 - > 0.9 Max VDIF-CLK : VDDQ+0.3 -> VDDQ+0.6 - DC characteristics is changed ISBZZ : 150 - > 128 - AC Characteristics are changed TAVKH / TDVKH / TWVKH / TSVKH : 0.4 / 0.5 / 0.5 - > 0.3 / 0.3 / 0.3 TKHAX / TKHDX / TKHWX / TKHSX : 0.5 / 0.5 / 0.5 - > 0.5 / 0.5 / 0.5
Draft Date
Jan. 2002 Jan. 2002
Remark
Advance Advance
Rev. 0.2
Feb. 2003
Advance
Rev. 0.3
- PACKAGE PIN CONFIGURATION are changed Numbering each SA pins. - AC Characteristics are changed TKHQV (-33) : 0.5 - > 0.6 - PIN CAPACITANCE is changed Add Clock Pin capacitance - Correct typo VDD -> VDDQ: in MODE CONTROL at page4 - Fill the themal Data - Remove 333MHz Bin - Add Pb free. - Modify package dimensions
Feb. 2003
Advance
Rev. 0.4
Mar. 2003
Advance
Rev. 0.5
May 2003
Advance
Rev. 0.6
Sep. 2003
Advance
Rev. 1.0
Sep. 2004
Final
Rev. 1.1 Rev. 1.2
Oct. 2005 Dec. 2005
Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
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Dec. 2005 Rev 1.2
K7P323666M K7P321866M
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
FEATURES
• 1Mx36 or 2Mx18 Organizations. • 2.5V Core/1.5V Output Power Supply (1.9V max VDDQ). • HSTL Input and Output Levels. • Differential, HSTL Clock Inputs K, K. • Synchronous Read and Write Operation • Registered Input and Registered Output • Internal Pipeline Latches to Support Late Write. • Byte Write Capability(four byte write selects, one for each 9bits) • Synchronous or Asynchronous Output Enable. • Power Down Mode via ZZ Signal. • Programmable Impedance Output Drivers. • JTAG 1149.1 Compatible Test Access port. • 119(7x17)Pin Ball Grid Array Package(14mmx22mm). Org. 1Mx36 2Mx18
www.DataSheet4U.com
1Mx36 & 2Mx18 SRAM
Part Number K7P323666M-H(G)C30 K7P323666M-H(G)C25 K7P321866M-H(G)C30 K7P321866M-H(G)C25
Maximum Frequency 300MHz 250MHz 300MHz 250MHz
Access Time 1.6 2.0 1.6 2.0
* G : Lead free package
FUNCTIONAL BLOCK DIAGRAM
SA[0:19] or SA[0:20] CK SS SW Latch SWx Register SWx Register Latch SW Register SW Register Read Address Register 1 Write Address Register 0 Row Decoder 1Mx36 or 2Mx18 Array Column Decoder Write/Read Circuit
SWx (x=a, b, c, d) or (x=a, b)
0
1 Data In Register
SS Register
SS Register
Data Out Register
G ZZ K K CK DQx[1:9] (x=a, b, c, d) or (x=a, b)
PIN DESCRIPTION
Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD VDDQ Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asynchronous Power Down Core Power Supply Output Power Supply Pin Name VREF M 1 , M2 G SS TCK TMS TDI TDO ZQ VSS NC Pin Description HSTL Input Reference Voltage Read Protocol Mode Pins ( M1=VSS, M2=VDDQ ) Asynchronous Output Enable Synchronous Select JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output Output Driver Impedance Control GND No Connection
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Dec. 2005 Rev 1.2
K7P323666M K7P321866M
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7P323666M(1Mx36)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc8 DQc6 VDDQ DQc3 DQc1 VDDQ DQd1 DQd3 VDDQ.