IS42S32800B

IS42S32800B 2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES · Concurrent auto precharge · Clock rate:166/143 MHz · Fully synchronous operation · Internal pipelined architecture · Four internal banks (2M x 32bit x 4bank) · Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write · Burst stop function · Individual byte controlled by DQM0-3 · Auto Refresh and Self Refresh · 4096 refresh cycles/64ms (15.6µs/row) · Single +3.3V ±0.3V power supply · Interface:LVTTL · Package: 86 Pin TSOP-2,0.50mm Pin Pitch 8x13mm, 90 Ball BGA, Ball pitch 0.8mm · Pb-free package is available. www.DataSheet4U.com ISSI July 2006 ® DESCRIPTION The ISSI IS42S32800B is a high-speed CMOS configured as a quad 2M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command The ISSI IS42S32800B provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions, either Auto or Self Ref...