Document
Integrated Circuit Systems, Inc.
ICS874003
www.DataSheet4U.com
PCI EXPRESS JITTER ATTENUATOR
FEATURES
• Three Differential LVDS output pairs • One Differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 160MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 35ps (maximum) • 3.3V operating supply • Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS874003 is a high performance Differential-to-LVDS Jitter Attenuator designed for HiPerClockS™ use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003 has 3 PLL bandwidth modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have than x25 multipliers, the ICS874003 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the FSEL pins.
IC S
PLL BANDWIDTH
BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~400kHz (default) 1 = PLL Bandwidth: ~800kHz
The ICS874003 uses ICS 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.
BLOCK DIAGRAM
OEA Pullup F_SELA Pulldown BW_SEL Float 0 = ~200kHz Float = ~400kHz 1 = ~800kHz CLK Pulldown nCLK Pullup QA0
PIN ASSIGNMENT
F_SELA 0 ÷5 (default) 1 ÷4
QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB1 nQB1 F_SELB OEB GND nCLK CLK OEA
nQA0 QA1
Phase Detector
VCO
490 - 640MHz
nQA1
ICS874003
F_SELB 0 ÷5 (default) 1 ÷4
QB0
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
M = ÷5 (fixed)
nQB0
G Package Top View
F_SELB Pulldown MR Pulldown OEB Pullup
874003AG
www.icst.com/products/hiperclocks.html
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REV. A JANUARY 25, 2006
Integrated Circuit Systems, Inc.
ICS874003
www.DataSheet4U.com
PCI EXPRESS JITTER ATTENUATOR
Type Output Power Output Input Description Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ PLL Bandwidth input. See Table 3B. Pulldown No connect. Analog supply pin. Frequency select pin for QAx/nQAx outputs. Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high impedance Pullup state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Frequency select pin for QBx/nQBx outputs. Pulldown LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 20 2, 19 3, 4 5 Name QA1, nQA1 VDDO QA0, nQA0 MR
6 7 8 9 10 11 12 13 14 15 16 17, 18
BW_SEL nc VDDA F_SELA VDD OEA CLK nCLK GND OEB F_SELB nQB1, QB1
Input Unused Power Input Power Input Input Input Power Input Input Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs OEA 0 1 OEB 0 1 HiZ Enabled Outputs QAx/nQAx QBx/nQBx HiZ Enabled
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs PLL_BW 0 1 Float PLL Bandwidth ~200kHz ~800kHz ~400kHz
874003AG
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