IS45S16320B

IS42S86400B IS42S16320B, IS45S16320B www.DataSheet4U.com 64M x 8, 32M x 16 SEPTEMBER 2009 512Mb SYNCHRONOUS DRAM FEATURES Clock frequency: 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Power supply Vdd Vddq IS42/45S16320B 3.3V 3.3V IS42S86400B LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh 8K refresh cycles every 64 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Available in 54-pin TSOP-II and 54-ball W-BGA (x16 only) Operating Temperature Range: Commercial: 0oC to +70oC Industrial: -40oC to +85oC Automotive, A1: -40oC to +85oC 3.3V 3.3V OVERVIEW ISSI's 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. IS42S86400B 16Mx8x4 Banks 54-pin TSOPII IS42/45S16320B 8M x16x4 Banks 54-pin TSOPII 54-ball W-BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 ...