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IS45S16100C1 Dataheets PDF



Part Number IS45S16100C1
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
Datasheet IS45S16100C1 DatasheetIS45S16100C1 Datasheet (PDF)

IS45S16100C1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • 4096 refresh cycles every 64 ms • Random column a.

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IS45S16100C1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Automotive Temperature Range Option A: 0oC to +70oC Option A1: -40oC to +85oC • Packages: 400-mil 50-pin TSOP-II, 60-ball fBGA • Lead-free package option www.DataSheet4U.com ISSI JANUARY 2006 ® DESCRIPTION ISSI’s 16Mb Synchronous DRAM IS45S16100C1 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 50-Pin TSOP (Type II) VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GND DQ15 IDQ14 GNDQ DQ13 DQ12 VDDQ DQ11 DQ10 GNDQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND PIN DESCRIPTIONS A0-A11 A0-A10 A11 A0-A7 DQ0 to DQ15 CLK CKE CS RAS Address Input Row Address Input Bank Select Address Column Address Input Data DQ System Clock Input Clock Enable Chip Select Row Address Strobe Command CAS WE LDQM UDQM VDD GND VDDQ GNDQ NC Column Address Strobe Command Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask Power Ground Power Supply for DQ Pin Ground for DQ Pin No Connection Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 01/03/06 1 IS45S16100C1 PIN CONFIGURATION ISSI 1 2 3 4 5 6 7 A B C D E F G H J K L M N P R ® www.DataSheet4U.com PACKAGE CODE: B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch) VSS DQ15 DQ14 VSSQ DQ13 VDDQ DQ12 DQ11 DQ10 VSSQ DQ9 VDDQ DQ8 NC NC NC DQ0 VDD VDDQ DQ1 VSSQ DQ2 DQ4 DQ3 VDDQ DQ5 VSSQ DQ6 NC NC LDQM RAS NC NC A0 A2 A3 DQ7 NC WE CAS CS NC A10 A1 VDD NC UDQM NC CKE A11 A8 A6 VSS CLK NC A9 A7 A5 A4 PIN DESCRIPTIONS A0-A10 A0-A7 A11 DQ0 to DQ15 CLK CKE CS RAS CAS 2 Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDQM, UDQM VDD Vss VDDQ VssQ NC Write Enable x16 Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 01/03/06 IS45S16100C1 PIN FUNCTIONS Pin No. 20 to 24 27 to 32 Symbol A0-A10 Type Input Pin Function (In Detail) ISSI www.DataSheet4U.com ® A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input and A0-A7 as column address inputs during read or write command input. A10 is also used to determine the precharge mode during other commands. If A10 is LOW during precharge command, the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged. When A10 is HIGH in read or write command cycle, the precharge starts automatically after the burst access. These signals become part of the OP CODE during mode register set command input. A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is selected. This signal becomes part of the OP CODE during mode register set command input. CAS, in conjunction with the RAS and WE, forms the device command. See the “Command Truth Table” item for details on device commands. The CKE input determines whether the CLK input is enabled within the device. When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid. When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether comma.


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