HYB18T512161B2F-20

June 2007 www.DataSheet4U.com HYB18T512161B2F–20/25 512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.1 Internet Data Sheet www.DataSheet4U.com HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512161B2F–20/25 Revision History: 2007-06, Rev. 1.1 Page All Subjects (major changes since last revision) Typo Changes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 05152007-ZYAH-ACMZ 2 Internet Data Sheet www.DataSheet4U.com HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family for graphics application and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: Data masks (DM) for write data 1.8 V ± 0.1V VDD for [–20/–25] 1.8 V ± 0.1V VDDQ for [–20/–25] Posted CAS by programmable additive latency for better DRAM organizations with 16 data in/outputs command and data bus efficiency Double Data Rate architecture: Off-Chip-Driver impedance adjustment (OCD) and On– two data transfers per clock cycle Die-Termination (ODT) for better signal quality. – four internal banks fo...