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PMWD30UN

NXP Semiconductors

Dual uTrenchMOS ultra low level FET

PMWD30UN Dual µTrenchMOS™ ultra low level FET M3D647 www.DataSheet4U.com Rev. 01 — 22 January 2003 Product data 1. P...


NXP Semiconductors

PMWD30UN

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PMWD30UN Dual µTrenchMOS™ ultra low level FET M3D647 www.DataSheet4U.com Rev. 01 — 22 January 2003 Product data 1. Product profile 1.1 Description Dual N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. Product availability: PMWD30UN in SOT530-1 (TSSOP8). 1.2 Features s Surface mounting package s Very low threshold s Low profile s Fast switching. 1.3 Applications s Portable appliances s Battery management s PCMCIA cards s Load switching. 1.4 Quick reference data s VDS ≤ 30 V s Ptot ≤ 2.3 W s ID ≤ 5 A s RDSon ≤ 33 mΩ 2. Pinning information Table 1: Pin 1 2,3 4 5 6,7 8 Pinning - SOT530-1, simplified outline and symbol Description drain1 (d1) source1 (s1) gate1 (g1) gate2 (g2) source2 (s2) drain2 (d2) 1 Top view 4 MBK885 Simplified outline 8 5 Symbol d1 d2 s1 g1 s2 g2 MSD901 SOT530-1 Philips Semiconductors PMWD30UN w ultra w wlow . level D a FET t a Dual µTrenchMOS™ S h e 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage gate-source voltage drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tsp = 25 °C peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs Tsp = 25 °C; VGS = 4.5 V; Figure 2 and 3 Tsp = 100 °C; VGS = 4.5 V; Figure 2 Tsp = 25 °C; pulsed; tp ≤ ...




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