DatasheetsPDF.com

UPD160062 Dataheets PDF



Part Number UPD160062
Manufacturers NEC
Logo NEC
Description 420-OUTPUT TFT-LCD SOURCE DRIVER
Datasheet UPD160062 DatasheetUPD160062 Datasheet (PDF)

DATA SHEET MOS INTEGRATED CIRCUIT µ PD160062 www.DataSheet4U.com 420-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALE) DESCRIPTION The µ PD160062 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scale. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the outpu.

  UPD160062   UPD160062



Document
DATA SHEET MOS INTEGRATED CIRCUIT µ PD160062 www.DataSheet4U.com 420-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALE) DESCRIPTION The µ PD160062 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scale. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 +0.1 V to VDD2 –0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to SXGA+ standard TFT-LCD panels. FEATURES • CMOS level input (2.3 to 3.6 V) • 420 outputs • Input of 6 bits (gray scale data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC) • Logic power supply voltage (VDD1) : 2.3 to 3.6 V • Driver power supply voltage (VDD2) : 8.0 to 9.0 V • High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V) • Output dynamic range VSS2 +0.1 V to VDD2 –0.1 V • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Input data inversion function (capable of controlling by each input port) (POL21, POL22) • Current consumption control function (LPC, HPC, Bcont) • Slim chip ORDERING INFORMATION Part Number Package TCP (TAB package) µ PD160062N-××× Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16449EJ1V0DS00 (1st edition) Date Published July 2003 NS CP(K) Printed in Japan 2002 µ PD160062 1. BLOCK DIAGRAM STHR R,/L CLK STB C1 C2 www.DataSheet4U.com 70-bit bidirectional shift register C69 C70 STHL VDD1 VSS1 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 POL21, POL22 Data register POL Latch VDD2 Level shifter VSS2 V0 to V9 D/A converter HPC LPC Bcont Voltage follower output S1 S2 S3 S420 Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 S2 S419 S420 V0 V4 V5 V9 Multiplexer 5 6-bit D/A converter 5 POL 2 Data Sheet S16449EJ1V0DS µ PD160062 3. PIN CONFIGURATION (µ PD160062N-xxx: TCP) (Copper Foil Surface, Face-up) www.DataSheet4U.com STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L V9 V8 V7 V6 V5 VDD2 VSS2 Bcont V4 V3 V2 V1 V0 HPC VSS1 LPC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR S420 S419 S418 S417 Copper Foil Surface S4 S3 S2 S1 Remark This figure does not specify the TCP package. Data Sheet S16449EJ1V0DS 3 µ PD160062 4. PIN FUNCTIONS Pin Symbol S1 to S420 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control Input The shift direction control pin of shift register. The shift directions of the shift registers are as follows. R,/L = H (right shift) : STHR input, S1 → S420, STHL output R,/L = L (left shift) : STHL input, S420 → S1, STHR output STHR Right shift start pulse I/O These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = H (right shift) : STHR input, STHL output STHL Left shift start pulse I/O R,/L = L (left shift) : STHL input, STHR output A H level should be input as the pulse of one cycle of the clock signal. If the start pulse input is more than 2 CLK, the first 1 CLK of the H level input is valid. CLK Shift clock Input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 70th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 72 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch Input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale vol.


UPD160061A UPD160062 UPD160083


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)