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AD7680 Dataheets PDF



Part Number AD7680
Manufacturers Analog Devices
Logo Analog Devices
Description 3mW + 100kSPS - 16-Bit ADC
Datasheet AD7680 DatasheetAD7680 Datasheet (PDF)

PRELIMINARY TECHNICAL DATA a Preliminary Technical Data FEATURES Fast Throughput Rate: 100kSPS Specified for VDD of 2.5 V to 5.25 V Low Power: 2.5mW typ at 100kSPS with 3V Supplies 15mW typ at 100kSPS with 5V Supplies Wide Input Bandwidth: 85dB SNR at 10kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI/QSPI/µWire/DSP Compatible Standby Mode: 0.5 µA max 6-Lead SOT-23, and 8-Lead MSOP Packages APPLICATIONS Battery-Powered Systems P.

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PRELIMINARY TECHNICAL DATA a Preliminary Technical Data FEATURES Fast Throughput Rate: 100kSPS Specified for VDD of 2.5 V to 5.25 V Low Power: 2.5mW typ at 100kSPS with 3V Supplies 15mW typ at 100kSPS with 5V Supplies Wide Input Bandwidth: 85dB SNR at 10kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI/QSPI/µWire/DSP Compatible Standby Mode: 0.5 µA max 6-Lead SOT-23, and 8-Lead MSOP Packages APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Remote Data Acquisition Systems High-Speed Modems Optical Sensors 3mW, 100kSPS, 16-Bit ADC in 6 Lead SOT-23 www.DataSheet4U.com AD7680 FUNCTIONAL BLOCK DIAGRAM VDD VIN T/H 16-BIT SUCCESSIVE APPROXIMATION ADC AD7680 SCLK CONTROL LOGIC SDATA +5 GND PRODUCT HIGHLIGHTS 1. First 16-Bit ADC in a SOT-23 package. 2. High Throughput with Low Power Consumption 3. Flexible Power/Serial Clock Speed Management The conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a powerdown mode is used while not converting. The part also features a shutdown mode to maximize power efficiency at lower throughput rates. Power consumption is 0.5µA max when in shutdown. 4. Reference derived from the power supply. 5. No Pipeline Delay The part features a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control. GENERAL DESCRIPTION The AD7680 is a 16-bit, fast, low power, successive-approximation ADC. The part operates from a single 2.5 V to 5.25 V power supply and features throughput rates up to 100kSPS. The part contains a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of 100kHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part. The AD7860 uses advanced design techniques to achieve very low-power dissipation at fast throughput rates. The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK frequency. REV. PrE 11/02 One Technology Way, P .O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. V = +2.5 V to +5.25 V, f = 2.5MHz, f = 100Ksps unless otherwise AD7680–SPECIFICATIONS1 (noted; T = T to T , unless otherwise noted.) DD SCLK SAMPLE A MIN MAX PRELIMINARY TECHNICAL DATA B Version1 3V 5V 81 82 85 -95 -99 Units www.DataSheet4U.com Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD)2 Signal to Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY No missing Codes Integral Nonlinearity3 Offset Error3 Gain Error3 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2,3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance2,3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation4 Normal Mode (Operational) Full Power-Down Test Conditions/Comments FIN = 10kHz Sine Wave 83 86 -95 -99 dB dB dB dB dB min min typ typ typ -90 -90 -90 -90 10 10 30 30 TBD TBD 15 ±4 ±5 ±5 14 ±4 ±5 ±10 dB typ dB typ ns max ps typ MHz typ @ 3 dB MHz typ @ 0.1 dB Bits min LSB max LSB max LSB max Volts µA max pF typ V min V max µA max pF max 0 to VDD ±1 30 2.4 0.4 ±1 10 2.4 0.8 ±1 10 Typically 10 nA, VIN = 0 V or VDD VDD -0.2 V min ISOURCE = 200 µA; VDD = 2.5 V to 5.25 V 0.4 V max ISINK =200 µA ±1 µA max 10 pF max Straight (Natural) Binary 8 9.6 500 400 100 +2.5/+5.25 0.95 0.9 0.5 µs max µs max ns max ns max kSPS V min/max Digital I/Ps = 0V or VDD. SCLK on or off. FSAMPLE = 100 kSPS SCLK on or off. 20 SCLK cycles with SCLK at 2.5MHz 24 SCLK cycles .


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