DatasheetsPDF.com

CYDM064A08 Dataheets PDF



Part Number CYDM064A08
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL Dual-Port Static RAM
Datasheet CYDM064A08 DatasheetCYDM064A08 Datasheet (PDF)

CYDM256A16, CYDM128A16, CYDM064A16, www.DataSheet4U.com CYDM128A08, CYDM064A08 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL® Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • 4/8/16K × 16 and 8/16K x 8 organization • High-speed access: 35 ns • Ultra Low operating power — Active: ICC = 15 mA (typical) at 55 ns — Active: ICC = 25 mA (typical) at 35 ns — Standby: ISB3 = 2 µA (typical) • Small footprint: Available in a 6x6 mm 100-.

  CYDM064A08   CYDM064A08


Document
CYDM256A16, CYDM128A16, CYDM064A16, www.DataSheet4U.com CYDM128A08, CYDM064A08 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL® Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • 4/8/16K × 16 and 8/16K x 8 organization • High-speed access: 35 ns • Ultra Low operating power — Active: ICC = 15 mA (typical) at 55 ns — Active: ICC = 25 mA (typical) at 35 ns — Standby: ISB3 = 2 µA (typical) • Small footprint: Available in a 6x6 mm 100-pin Lead(Pb)-free fBGA • Supports 1.8V, 2.5V, and 3.0V I/Os • Full asynchronous operation • Automatic power-down • Pin select for Master or Slave • Expandable data bus to 32 bits with Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • Input Read Registers and Output Drive Registers • INT flag for port-to-port communication • Separate upper-byte and lower-byte control • Industrial temperature ranges Selection Guide for 1.8V CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 35 25 2 2 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 55 15 2 2 Unit ns mA µA µA Selection Guide for 2.5V CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 35 39 6 4 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 55 28 6 4 Unit ns mA µA µA Selection Guide for 3.0V CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -35 Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 35 49 7 6 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 -55 55 42 7 6 Unit ns mA µA µA Cypress Semiconductor Corporation Document #: 38-06081 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 31, 2005 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, www.DataSheet4U.com CYDM064A08 I/O[15:0]L UBL LBL IO Control IO Control I/O[15:0]R UBR LBR 16K X 16 Dual Ported Array Address Decode Address Decode A[13:0]L CE L OE L R/W L SEML BUSY L INTL Mailboxes Interrupt Arbitration Semaphore A [13:0]R CE R OE R R/W R SEMR BUSY R INTR M/S IRR0 ,IRR1 CEL OEL R/WL Input Read Register and Output Drive Register CE R OE R R/W R ODR0 - ODR4 SFEN Figure 1. Top Level Block Diagram[1,2] Notes: 1. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices. 2. BUSY is an output in master mode and an input in slave mode. Document #: 38-06081 Rev. *F Page 2 of 25 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, www.DataSheet4U.com CYDM064A08 Pin Configurations [3, 4, 5, 6, 7, 8] 100-Ball 0.5-mm Pitch BGA Top View CYDM064A16/CYDM128A16/CYDM256A16 1 A B C A5R A3R A0R 2 A8R A4R A1R 3 A11R A7R A2R 4 UBR A9R A6R INTR INTL A1L A12L[3] LBL IRR0[5] UBL 4 5 VSS CER LBR A10R VSS VCC OEL CEL VCC SEML 5 6 SEMR R/WR 7 I/O15R OER 8 I/O12R VCC I/O11R I/O8R VCC I/O0R I/O12L NC [7] I/O6L I/O2L 8 9 I/O10R I/O9R I/O7R I/O5R I/O1R I/O15L I/O14L NC[7] I/O8L I/O5L 9 10 VSS I/O6R VSS I/O2R VSS VCC A B C D E F IRR1[6] I/O14R A12R[3] VSS VSS I/O3L I/O1L VSS R/WL 6 I/O13R I/O4R I/O3R I/O11L VCC I/O4L I/O0L 7 D ODR4 ODR2 BUSYR E VSS M/S ODR3 F SFEN [8] ODR1 BUSYL G ODR0 H J K A0L A3L A6L 1 A2L A4L A7L A8L 2 A5L A9L A10L A11L 3 I/O13L G I/O10L H I/O9L I/O7L 10 J K Notes: 3. A12L and A12R are NC pins for CYDM064A16. 4. IRR functionality is not supported for the CYDM256A16 device. 5. This pin is A13L for CYDM256A16 device. 6. This pin is A13R for CYDM256A16 device. 7. Leave this pin unconnected. No trace or power component can be connected to this pin. 8. IRR functionality not supported for the CYDM256A16 device. Connect this pin to VCC. Document #: 38-06081 Rev. *F Page 3 of 25 CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, www.DataSheet4U.com CYDM064A08 Pin Configurations (continued)[7, 9, 10, 11,12, 13] 100-Ball 0.5-mm Pitch BGA Top View CYDM064A08/CYDM128A08 1 A B C A5R A3R A0R 2 A8R A4R A1R 3 A11R A7R A2R 4 VCC A9R A6R INTR INTL A1L A12L VSS IRR0 [10] 5 VSS CER VSS A10R VSS VCC OEL CEL VCC SEML 5 6 SEMR R/WR IRR1[11] A12R VSS VSS I/O3L I/O1L VSS R/WL 6 7 VSS OER VSS VSS I/O4R I/O3R VSS VCC I/O4L I/O0L 7 8 VSS VCC VSS VSS VCC I/O0R VSS NC[12] I/O6L I/O2L 8 9 VSS VSS I/O7R I/O5R I/O1R VSS VSS NC[12] VSS I/O5L 9 10 VSS I/O6R VSS I/O2R VSS VCC VSS VSS VSS I/O7L 10 A B C D E F G H J K D ODR4 ODR2 BUSYR E VSS M/ S ODR3 F SFEN[13] ODR1 BUSYL G ODR0 H J K A0L A3L A6L 1 A2L A4L A7L A8L 2 A5L A9L A10L A11L 3 VCC 4 Notes: 9. IRR functionality is not supported for the CYDM128A08 device. 10. This pin is A13L for CYDM128A08 devices. 11. This pin is A13R for CYDM128A08 devices. 12. Leave this pin unconnected. No trace or power component can be connected to this pin. 13. IRR functionality is not suppo.


SC68C752B CYDM064A08 CYDM256A16


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)