IS61LPS25672A

IS61vPS25672A IS61lPS25672A IS61vPS51236A IS61lPS51236A IS61vPS102418A IS61lPS102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM JULY 2017 FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth ex- pansion and address pipelining Common data inputs and data outputs Auto Power-down during deselect Single cycle deselect Snooze MODE for reduced-power standby JTAG Boundary Scan for PBGA package Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball PBGA, and 209-ball (x72) packages Lead-free available DESCRIPTION The  ISSI IS61LPS/VPS51236A, IS61LPS/VPS102418A, and IS61LPS/VPS25672A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/VPS51236A is organized as 524,288 words by 36 bits, the IS61LPS/VPS102418A is organized as 1,048,576 words by 18 bits, and the IS61LPS/ VPS25672A is organized as 262,144 words by 72 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers cont...