ICS858012

PRELIMINARY Integrated Circuit Systems, Inc. www.DataSheet4U.com ICS858012 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER FEATURES Two differential LVPECL outputs One differential LVPECL clock input IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Output frequency: 2GHz (typical) Output skew: <15ps (typical) Part-to-part skew: TBD Additive phase jitter, RMS: TBD Propagation delay: 350ps (typical) Operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V -40°C to 85°C ambient operating temperature Availabe in both standard and lead-free RoHS compliant packages GENERAL DESCRIPTION The ICS858012 is a high speed 1-to-2 Differentialto-2.5V, 3.3V LVPECL Fanout Buffer and is a HiPerClockS™ member of the HiPerClockS™ family of high performance clock solutions from ICS. The ICS858012 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, LVHSTL and HCSL to be easily interfaced to the input with minimal use of external components. The ICS858012 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. IC S BLOCK DIAGRAM PIN ASSIGNMENT VCC IN 1 VT 2 Q0 nQ0 VREF_AC 3 nIN 4 16 15 14 13 1...