Document
ICX255AL
Diagonal 6mm (Type 1/3) CCD Image Sensor for CCIR B/W Video Cameras
Description The ICX255AL is an interline CCD solid-state image sensor suitable for CCIR B/W video cameras with a diagonal 6mm (Type 1/3) system. Compared with the current product ICX055BL, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically from visible light region to near infrared light region through the adoption of EXview HAD CCDTM technology. This chip features a field period readout system and an electronic shutter with variable charge-storage time. Features • Sensitivity in near infrared light region (+8dB compared with the ICX055BL, λ = 945nm) • High sensitivity (+6dB compared with the ICX055BL, no IR cut filter) • Low smear (–20dB compared with the ICX055BL) • High D range (+3dB compared with the ICX055BL) V • High S/N • Low dark current • Excellent antiblooming characteristics 7 • Continuous variable-speed shutter • No voltage adjustment (Reset gate and substrate bias are not adjusted.) • Reset gate: 5V drive • Horizontal register: 5V drive 16 pin DIP (Plastic)
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Pin 1 1
14 H 30
Pin 9
Optical black position (Top View)
Device Structure • Interline CCD image sensor • Image size: Diagonal 6mm (Type 1/3) • Number of effective pixels: 500 (H) × 582 (V) approx. 290K pixels • Total number of pixels: 537 (H) × 597 (V) approx. 320K pixels • Chip size: 6.00mm (H) × 4.96mm (V) • Unit cell size: 9.8µm (H) × 6.3µm (V) • Optical black: Horizontal (H) direction : Front 7 pixels, rear 30 pixels Vertical (V) direction : Front 14 pixels, rear 1 pixel • Number of dummy bits: Horizontal 16 Vertical 1 (even fields only) • Substrate material: Silicon
TM
∗ EXview HAD CCD is a trademark of Sony Corporation. EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of HAD (Hole-Accumulation-Diode) sensor. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99522-PS
ICX255AL
Block Diagram and Pin Configuration (Top View)
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VOUT GND Vφ1 Vφ3
2
8
7
6
5
Vφ2
4
3
Vertical Register
Horizontal Register Note) : Photo sensor
9
10
11
12
13
14
15
GND
φSUB
Hφ1
VDD
φRG
Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol Vφ4 Vφ3 Vφ2 Vφ1 GND NC NC VOUT Signal output
Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND
Pin No. 9 10 11 12 13 14 15 16
Hφ2
VL
NC
Vφ 4
1 Note) 16
NC
NC
Symbol VDD GND φSUB VL φRG NC Hφ1 Hφ2
Description Supply voltage GND Substrate clock Protective transistor bias Reset gate clock
Horizontal register transfer clock Horizontal register transfer clock
Absolute Maximum Ratings Item VDD, VOUT, φRG – φSUB Against φSUB Vφ1, Vφ3 – φSUB Vφ2, Vφ4, VL – φSUB Hφ1, Hφ2, GND – φSUB VDD, VOUT, φRG – GND Against GND Vφ1, Vφ2, Vφ3, Vφ4 – GND Hφ1, Hφ2 – GND Against VL Vφ1, Vφ3 – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Between input clock pins Storage temperature Operating temperature ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –2– Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4 Ratings –40 to +8 –50 to +15 –50 to +0.3 –40 to +0.3 –0.3 to +20 –10 to +18 –10 to +6 –0.3 to +28 –0.3 to +15 to +15 –6 to +6 –14 to +14 –30 to +80 –10 to +60 Unit V V V V V V V V V V V V °C °C ∗1 Remarks
ICX255AL www.DataSheet4U.com
Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL φSUB φRG Min. 14.55 Typ. 15.0 ∗1 ∗2 ∗2 Max. 15.45 Unit V Remarks
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.
DC Characteristics Item Supply current Symbol IDD Min. Typ. 3 Max. 6 Unit mA Remarks
Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VφV Vertical transfer clock voltage VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage VφH VHL VφRG Reset gate clock voltage VRGLH – VRGLL VRGL – VRGLm Substrate clock voltage VφSUB 21.0 22.0 4.75 –0.05 4.5 5.0 0 5.0 Min. 14.55 –0.05 –0.2 –8.0 6.3 –0.25 –0.25 Typ. 15.0 0 0 –7.0 7.0 Max. 15.45 0.05 0.05 –6.5 8.05 0.1 0.1 0.3 0.3 0.3 0.3 5.25 0.05 5.5 0.4 0.5 23.5 Unit V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Input through 0.1µF capacitance Low-level coupling Low-level coupling High-level.