Common Clock and Reset High-Speed Silicon-Gate CMOS
TECHNICAL DATA
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KK74ACT174
Hex D Flip-Flop with Common Clock and Reset
High-Speed Silicon-Gate CMO...
Description
TECHNICAL DATA
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KK74ACT174
Hex D Flip-Flop with Common Clock and Reset
High-Speed Silicon-Gate CMOS
The KK74ACT174 is identical in pinout to the LS/ALS174, HC/HCT174. The KK74ACT174 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low. TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 µA; 0.1 µA @ 25°C Outputs Source/Sink 24 mA
ORDERING INFORMATION KK74ACT174N Plastic KK74ACT174D SOIC TA = -40° to 85° C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Reset L PIN 16=VCC PIN 8 = GND H H H H X = Don’t care L Clock X D X H L X X Output Q L H L no change no change
1
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KK74ACT174
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 5...
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