HYB39S16160CT-10

www.DataSheet4U.com 16 MBit Synchronous DRAM HYB 39S16400/800/160CT-8/-10 High Performance: -8 -10 100 10 7 12 8 Units MHz ns ns ns ns fCK(MAX.) tCK3 tAC3 tCK2 tAC2 125 8 6 10 6 Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Data Mask for Read/Write control Dual Data Mask for byte control (× 16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 4096 refresh cycles/64 ms Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: P-TSOPI-44 400mil width (× 4, × 8) P-TSOPII-50 400mil width (× 16 ) -8 version for PC100 applications Fully Synchronous to Positive Clock Edge 0 to 70 °C operating temperature Dual Banks controlled by A11 ( Bank Select) Programmable CAS Latency: 2, 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 Full page (optional) for sequencial wrap around The HYB39S16400/800/160CT are dual bank Synchronous DRAM’s based on SIEMENS 0.25 µm process and organized as 2 banks × 2 MBit × 4, 2 banks × 1 MBit × 8 and 2 banks × 512 kbit × 16 respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’ advanced 16 MBit DRAM process technology. The device is designed to comply with all ...