HYB39S16160CT-6

www.DataSheet4U.com HYB39S16160CT-6/-7 16MBit Synchronous DRAM 1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications High Performance: -6 fCKmax @ CL=3 tCK3 tAC3 fCKmax @ CL=2 tCK2 tAC2 166 6 5 125 8 6 -7 143 7 5.5 115 9 6 Units MHz ns ns MHz ns ns full page(optional) for sequencial wrap around Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge Data Mask for Read / Write control Dual Data Mask for byte control ( x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 4096 refresh cycles / 64 ms Latency 2 @ 125 MHz Latency 3 @ 166 MHz Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface Plastic Packages: P-TSOPII-50 400mil width ( x16 ) Fully Synchronous to Positive Clock Edge 0 to 70 °C operating temperature Dual Banks controlled by A11 ( Bank Select) Programmable CAS Latency : 2, 3 Programmable Wrap Sequence : Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 The HYB39S16160CT-6/-7 are high speed dual bank Synchronous DRAM’s based on SIEMENS 0.25µm process and organized as 2 banks x 512kbit x 16. These synchronous devices achieve high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’ advanced 16MBit DRAM process technology. The device is designed to comply ...