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HYB39S13620TQ-8 Dataheets PDF



Part Number HYB39S13620TQ-8
Manufacturers Siemens Semiconductor
Logo Siemens Semiconductor
Description Special Mode Registers Two color registers Burst Read
Datasheet HYB39S13620TQ-8 DatasheetHYB39S13620TQ-8 Datasheet (PDF)

www.DataSheet4U.com Overview HYB 39S13620TQ-6/-7/-8 • High Performance: -6 -7 125 2 8 5.5 -7 125 3 7 5.5 -8 125 3 8 6 Units MHz − ns ns • Special Mode Registers • Two color registers • Burst Read with Single Write Operation • Block Write and Write-per-Bit Capability • Byte controlled by DQM0-3 • Auto Precharge and Auto Refresh Modes • Suspend Mode and Power Down Mode • 2k refresh cycles/32 ms • tAC = 5 ns • tSETUP/tHOLD = 2 ns/1 ns • Latency 2 @ 125 MHz • Random Column Address every CLK (1-N.

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www.DataSheet4U.com Overview HYB 39S13620TQ-6/-7/-8 • High Performance: -6 -7 125 2 8 5.5 -7 125 3 7 5.5 -8 125 3 8 6 Units MHz − ns ns • Special Mode Registers • Two color registers • Burst Read with Single Write Operation • Block Write and Write-per-Bit Capability • Byte controlled by DQM0-3 • Auto Precharge and Auto Refresh Modes • Suspend Mode and Power Down Mode • 2k refresh cycles/32 ms • tAC = 5 ns • tSETUP/tHOLD = 2 ns/1 ns • Latency 2 @ 125 MHz • Random Column Address every CLK (1-N Rule) • Single 3.3 V ± 0.3 V Power Supply • LVTTL compatible inputs and outputs fCK latency 166 3 6 5.5 tCK3 tAC3 • Single Pulsed RAS Interface • Programmable CAS Latency: 2, 3 • Fully Synchronous to Positive Clock Edge • Programmable Wrap Sequence: Sequential or Interleave • Programmable Burst Length: 1, 2, 4, 8 and full page for sequential 1, 2, 4, 8 for interleave The HYB 39S163200TQ are dual bank Synchronous Graphics DRAM’s (SGRAM) organized as 2 banks × 256 Kbit × 32 with built-in graphics features. These synchronous devices achieve high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with an advanced 64MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous graphics DRAM products, both electrically and mechanically. RAS, CAS, WE, DSF and CS are pulsed signals which are examined at the positive edge of each externally applied clock. Internal chip operating modes are defined by combinations of these signals. A ten bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Ten row address bits (A0 - A9) and a bank select BA are strobed with RAS. Column address bits plus a bank select are strobed with CAS. Prior to any access operation, the CAS latency, burst length and burst sequence must be programmed into the device by address inputs during a mode register set cycle. An Auto Precharge function may be enabled to provide a self-timed row precharge. This is initiated at the end of the burst sequence. In addition, it features the write per bit, the block write and the masked block write Semiconductor Group 1 1998-10-01 HYB 39S16320TQ-6/-7/-8 www.DataSheet4U.com functions. By having a programmable Mode register and Special Mode register, the system can select the best suitable modes to maximize its performance. Operating the two memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply and are available in 100 pin TQFP package. Ordering Information Type SDR LVTTL-Version HYB 39S16320TQ-6 HYB 39S16320TQ-7 HYB 39S16320TQ-8 HYB 39S16320TQ-10 Features • All signals fully synchronous to the positiv edge of the system clock • Programmable burst lengths: 1, 2, 4, 8 or full page • Burst data transfer in sequential or interleaved order • Burst read with single write • Programmable CAS latency: 2, 3 • 8 column block write and write-per-bit modes • Independent byte operation via DQM 0 …3 interface • Auto precharge and auto refresh modes • 2k refresh cycles/32 ms • LVTTL compatible I/O • Hidden auto precharge for read bursts on request on request on request on request TQFP-100-1 TQFP-100-1 TQFP-100-1 TQFP-100-1 256k × 2 × 32 SGRAM 256k × 2 × 32 SGRAM 256k × 2 × 32 SGRAM 256k × 2 × 32 SGRAM Ordering Code Package Description Semiconductor Group 2 1998-10-01 HYB 39S16320TQ-6/-7/-8 www.DataSheet4U.com 100 pin TQFP 20 × 14 mm2 0.65 mm pitch (Marking side) DQ2 V SSQ DQ1 DQ0 V DD N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. V SS DQ31 DQ30 V SSQ DQ29 DQ3 V DDQ DQ4 DQ5 V SSQ DQ6 DQ7 V DDQ DQ16 DQ17 V SSQ DQ18 DQ19 V DDQ V DD V SS DQ20 DQ21 V SSQ DQ22 DQ23 V DDQ DQM0 DQM2 WE CAS RAS CS BA A9 100 1 95 90 85 80 5 75 10 70 15 65 20 60 25 55 30 35 40 45 50 DQ28 V DDQ DQ27 DQ26 V SSQ DQ25 DQ24 V DDQ D15 D14 V SSQ D13 D12 V DDQ V SS V DD DQ11 DQ10 V SSQ DQ9 DQ8 V DDQ MCH DQM3 DQM1 CLK CKE DSF N.C. A8 / AP A0 A1 A2 A3 V DD N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. V SS A4 A5 A6 A7 SPP03942 Pin Configuration Semiconductor Group 3 1998-10-01 HYB 39S16320TQ-6/-7/-8 www.DataSheet4U.com Pin Definitions and Functions CLK CKE CS RAS CAS WE A0 - A9 A8 - AP BA Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Auto Precharge Bank Select DQ0 to DQ31 DataInput/Output Power (+ 3.3 V) Ground Power for DQ’s (+ 3.3 V) Ground for DQ’s Not connected Special Function Enable Must Connect High DQM0 to DQM3 Data Mask VDD VSS VDDQ VSSQ NC DSF MCH Semiconductor Group 4 1998-10-01 HYB 39S16320TQ-6/-7/-8 www.DataSheet4U.co.


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